// SPDX-License-Identifier: MIT
`timescale 1ns/1ps
module tb;
  logic clk=0; integer a=1,b=2;
  always @(posedge clk) begin a<=b; b<=a; end
  initial begin
    #5; clk=1; #1; $display("OBS a=%0d b=%0d",a,b);
    $finish;
  end
endmodule