// SPDX-License-Identifier: MIT
`timescale 1ns/1ps
module tb;
  logic clk=0; logic [3:0] a=0,b=0,c=0;
  always @(posedge clk) begin a<=a+1'b1; b<=a; c<=b; end
  initial begin
    repeat(3) begin #5; clk=1; #1; $display("OBS a=%0d b=%0d c=%0d",a,b,c); #4; clk=0; end
    $finish;
  end
endmodule