{
  "dataset_id": "D3",
  "title": "HDL simulator observations: thirty original fixtures",
  "version": "2026-10-24-p6",
  "licence": "CC-BY-4.0",
  "licence_url": "https://creativecommons.org/licenses/by/4.0/",
  "attribution": "HDL simulator observations \u2014 original compilation, 2026-10-24",
  "fixture_count": 30,
  "tool_count": 2,
  "pipeline_count": 60,
  "executions_including_repeat": 120,
  "execution_environment": {
    "os": "macOS 27.0.1 build 26A434",
    "architecture": "arm64",
    "compiler": "Apple clang version 21.0.0 (clang-2100.3.34.2)",
    "local_date": "2026-10-24",
    "tools": {
      "icarus": "Icarus Verilog 13.0 stable v13_0",
      "verilator": "Verilator 5.052 2026-09-05 rev vUNKNOWN-built20260905"
    },
    "configuration": {
      "icarus": [
        "-g2012",
        "-gstrict-expr-width",
        "-Wall"
      ],
      "verilator": [
        "--timing",
        "--language 1800-2012",
        "--x-assign 0",
        "--x-initial 0",
        "-Wno-fatal"
      ],
      "purpose": "Declared configurations, not defaults or language conformance verdicts."
    }
  },
  "summary": {
    "compiled": 60,
    "executed": 60,
    "repeat_payloads_equal": 60,
    "matching_fixture_payloads": 20,
    "different_fixture_payloads": 10,
    "different_fixture_ids": [
      "F01",
      "F02",
      "F13",
      "F14",
      "F15",
      "F16",
      "F18",
      "F19",
      "F29",
      "F30"
    ],
    "compile_warning_pipeline_count": 3
  },
  "comparison_rule": "Compare only literal lines beginning OBS. Full literal stdout/stderr and return codes remain in every observation; finish banners are not normalized into semantic differences.",
  "seed_scope": "F28 is an explicit portable modulo-arithmetic sequence. F29/F30 pin built-in seeds but do not assume matching algorithms across tools.",
  "rows": [
    {
      "id": "F01",
      "title": "Explicit unknown assignment",
      "category": "four-state",
      "source": "harness/hdl-simulator-observations/fixtures/F01.sv",
      "source_sha256": "0aff1f827d4027a3be001c9989386f2f8229ae1162083ac9326bda99c1aba444",
      "origin": "Original project-authored fixture; first five concepts extend earlier original project fixtures.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS value=10x1 unknown=1\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS value=10x1 unknown=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:32:59.013749+00:00",
          "log": "harness/hdl-simulator-observations/logs/F01-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS value=1001 unknown=0\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS value=1001 unknown=0"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:08.563729+00:00",
          "log": "harness/hdl-simulator-observations/logs/F01-verilator.json"
        }
      },
      "observed_payload_equal": false,
      "interpretation": "Unknown or initialization behavior differs under the declared Verilator zero policies and Icarus four-state representation.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F01.sv"
    },
    {
      "id": "F02",
      "title": "Uninitialized register",
      "category": "initialization",
      "source": "harness/hdl-simulator-observations/fixtures/F02.sv",
      "source_sha256": "8803165c30ab4298001506d849867f3711ea5d0bc2a7aeb2faf5a8cdc6600d1a",
      "origin": "Original project-authored fixture; first five concepts extend earlier original project fixtures.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS value=xxxxxxxx unknown=1\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS value=xxxxxxxx unknown=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:32:59.055145+00:00",
          "log": "harness/hdl-simulator-observations/logs/F02-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS value=00000000 unknown=0\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS value=00000000 unknown=0"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:08.565556+00:00",
          "log": "harness/hdl-simulator-observations/logs/F02-verilator.json"
        }
      },
      "observed_payload_equal": false,
      "interpretation": "Unknown or initialization behavior differs under the declared Verilator zero policies and Icarus four-state representation.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F02.sv"
    },
    {
      "id": "F03",
      "title": "Mixed signed comparison",
      "category": "signedness",
      "source": "harness/hdl-simulator-observations/fixtures/F03.sv",
      "source_sha256": "92a19e3cef2946572ca028201862dc453d767e7dd95e5c938d49b2e313ad1679",
      "origin": "Original project-authored fixture; first five concepts extend earlier original project fixtures.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS mixed_less=0 cast_less=1\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS mixed_less=0 cast_less=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:08.617340+00:00",
          "log": "harness/hdl-simulator-observations/logs/F03-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS mixed_less=0 cast_less=1\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS mixed_less=0 cast_less=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:15.480575+00:00",
          "log": "harness/hdl-simulator-observations/logs/F03-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F03.sv"
    },
    {
      "id": "F04",
      "title": "Assignment-width truncation",
      "category": "width",
      "source": "harness/hdl-simulator-observations/fixtures/F04.sv",
      "source_sha256": "a14d8794cf0adc49a579a9f7e222f9bcd956088bec32763aeed2be0751a2be6c",
      "origin": "Original project-authored fixture; first five concepts extend earlier original project fixtures.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS narrow=1 wide=17\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS narrow=1 wide=17"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:08.673077+00:00",
          "log": "harness/hdl-simulator-observations/logs/F04-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS narrow=1 wide=17\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS narrow=1 wide=17"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:15.579529+00:00",
          "log": "harness/hdl-simulator-observations/logs/F04-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F04.sv"
    },
    {
      "id": "F05",
      "title": "Clocked nonblocking update",
      "category": "ordering",
      "source": "harness/hdl-simulator-observations/fixtures/F05.sv",
      "source_sha256": "c355074c07707bcf6b2c0ab149ebd365ee5e68e0ee1e118930ef3856b0e07efd",
      "origin": "Original project-authored fixture; first five concepts extend earlier original project fixtures.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS a=1 b=0\nfixture.sv:8: $finish called at 6000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=1 b=0"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:15.520381+00:00",
          "log": "harness/hdl-simulator-observations/logs/F05-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS a=1 b=0\n- fixture.sv:8: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=1 b=0"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:24.579217+00:00",
          "log": "harness/hdl-simulator-observations/logs/F05-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F05.sv"
    },
    {
      "id": "F06",
      "title": "Signed extension",
      "category": "signedness",
      "source": "harness/hdl-simulator-observations/fixtures/F06.sv",
      "source_sha256": "743ce75b82f46170c6a034f3fb0ac4c5d55253c536586b781614b4f24c379831",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS a=-8 b=-8 bits=fff8\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=-8 b=-8 bits=fff8"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:15.615637+00:00",
          "log": "harness/hdl-simulator-observations/logs/F06-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "%Warning-WIDTHEXPAND: fixture.sv:6:12: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 8 bits.\n                                     : ... note: In instance 'tb'\n    6 |     a=-8; b=a; #1; $display(\"OBS a=%0d b=%0d bits=%h\",a,b,b);\n      |            ^\n                      ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.052\n                      ... Use \"/* verilator lint_off WIDTHEXPAND */\" and lint_on around source to disable this message.\n",
          "runtime_stdout": "OBS a=-8 b=-8 bits=fff8\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=-8 b=-8 bits=fff8"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:24.629802+00:00",
          "log": "harness/hdl-simulator-observations/logs/F06-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F06.sv"
    },
    {
      "id": "F07",
      "title": "Unsigned extension",
      "category": "signedness",
      "source": "harness/hdl-simulator-observations/fixtures/F07.sv",
      "source_sha256": "2975eec2dba42312e02813fcd81687278328a81cbbe247c133b35f9322cd60d9",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS a=248 b=248 bits=00f8\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=248 b=248 bits=00f8"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:24.627965+00:00",
          "log": "harness/hdl-simulator-observations/logs/F07-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "%Warning-WIDTHEXPAND: fixture.sv:6:15: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 8 bits.\n                                     : ... note: In instance 'tb'\n    6 |     a=8'hf8; b=a; #1; $display(\"OBS a=%0d b=%0d bits=%h\",a,b,b);\n      |               ^\n                      ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.052\n                      ... Use \"/* verilator lint_off WIDTHEXPAND */\" and lint_on around source to disable this message.\n",
          "runtime_stdout": "OBS a=248 b=248 bits=00f8\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=248 b=248 bits=00f8"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:32.437935+00:00",
          "log": "harness/hdl-simulator-observations/logs/F07-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F07.sv"
    },
    {
      "id": "F08",
      "title": "Logical and arithmetic shifts",
      "category": "signedness",
      "source": "harness/hdl-simulator-observations/fixtures/F08.sv",
      "source_sha256": "76fb8929d509eb5e91a9661266a2fa8b35f71490079d31706b628e3614676138",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS logical=3c arithmetic=fc\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS logical=3c arithmetic=fc"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:24.687993+00:00",
          "log": "harness/hdl-simulator-observations/logs/F08-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS logical=3c arithmetic=fc\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS logical=3c arithmetic=fc"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:32.436170+00:00",
          "log": "harness/hdl-simulator-observations/logs/F08-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F08.sv"
    },
    {
      "id": "F09",
      "title": "Unsized literal widths",
      "category": "width",
      "source": "harness/hdl-simulator-observations/fixtures/F09.sv",
      "source_sha256": "f7bb3ef047c2ef7b4021936d0eb665a748db0d00240613f543fd9f4076431c8e",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS decimal_bits=32 hex_bits=32 value=1\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS decimal_bits=32 hex_bits=32 value=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:32.486218+00:00",
          "log": "harness/hdl-simulator-observations/logs/F09-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS decimal_bits=32 hex_bits=32 value=1\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS decimal_bits=32 hex_bits=32 value=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:40.436349+00:00",
          "log": "harness/hdl-simulator-observations/logs/F09-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F09.sv"
    },
    {
      "id": "F10",
      "title": "Expression assignment context",
      "category": "width",
      "source": "harness/hdl-simulator-observations/fixtures/F10.sv",
      "source_sha256": "1c7dcbf188daa976f49977bb8ca0afbb5fb6b3b2f47317005be9276c7a1da5b0",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS narrow=0 wide=16\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS narrow=0 wide=16"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:32.540313+00:00",
          "log": "harness/hdl-simulator-observations/logs/F10-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS narrow=0 wide=16\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS narrow=0 wide=16"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:40.473444+00:00",
          "log": "harness/hdl-simulator-observations/logs/F10-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F10.sv"
    },
    {
      "id": "F11",
      "title": "Concatenation unsigned comparison",
      "category": "signedness",
      "source": "harness/hdl-simulator-observations/fixtures/F11.sv",
      "source_sha256": "d2e526eaed1907a17b8ddfdeb18095ff76c05783a5d59055e271633ef0a95bc7",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS signed_less=1 concat_less=0\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS signed_less=1 concat_less=0"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:40.481978+00:00",
          "log": "harness/hdl-simulator-observations/logs/F11-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "%Warning-UNSIGNED: fixture.sv:6:69: Comparison is constant due to unsigned arithmetic\n                                  : ... note: In instance 'tb'\n    6 |     a=-1; #1; $display(\"OBS signed_less=%0d concat_less=%0d\",a<0,{a}<0);\n      |                                                                     ^\n                   ... For warning description see https://verilator.org/warn/UNSIGNED?v=5.052\n                   ... Use \"/* verilator lint_off UNSIGNED */\" and lint_on around source to disable this message.\n",
          "runtime_stdout": "OBS signed_less=1 concat_less=0\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS signed_less=1 concat_less=0"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:48.246740+00:00",
          "log": "harness/hdl-simulator-observations/logs/F11-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F11.sv"
    },
    {
      "id": "F12",
      "title": "Explicit signed cast",
      "category": "signedness",
      "source": "harness/hdl-simulator-observations/fixtures/F12.sv",
      "source_sha256": "b0bc235dc7777b9b6e1839efc2242060e70a089ef0dee27b67bdf3ceedcb1953",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS unsigned=255 signed=-1\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS unsigned=255 signed=-1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:40.534576+00:00",
          "log": "harness/hdl-simulator-observations/logs/F12-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS unsigned=255 signed=-1\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS unsigned=255 signed=-1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:48.385237+00:00",
          "log": "harness/hdl-simulator-observations/logs/F12-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F12.sv"
    },
    {
      "id": "F13",
      "title": "Unknown condition in if",
      "category": "four-state",
      "source": "harness/hdl-simulator-observations/fixtures/F13.sv",
      "source_sha256": "3e85a4a1f7884bcf1f1f9d902b2a320e6aa9cf54bfca1040ff77a44f1aa1abb4",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS sel=x branch=2\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS sel=x branch=2"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:48.294444+00:00",
          "log": "harness/hdl-simulator-observations/logs/F13-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS sel=0 branch=2\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS sel=0 branch=2"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:54.989274+00:00",
          "log": "harness/hdl-simulator-observations/logs/F13-verilator.json"
        }
      },
      "observed_payload_equal": false,
      "interpretation": "Unknown or initialization behavior differs under the declared Verilator zero policies and Icarus four-state representation.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F13.sv"
    },
    {
      "id": "F14",
      "title": "Unknown conditional bit merge",
      "category": "four-state",
      "source": "harness/hdl-simulator-observations/fixtures/F14.sv",
      "source_sha256": "e0101f0529a119e45821b434c148b25cab2554419f49d19e57a25013a39361a8",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS value=10xx\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS value=10xx"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:48.425701+00:00",
          "log": "harness/hdl-simulator-observations/logs/F14-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS value=1001\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS value=1001"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:55.146251+00:00",
          "log": "harness/hdl-simulator-observations/logs/F14-verilator.json"
        }
      },
      "observed_payload_equal": false,
      "interpretation": "Unknown or initialization behavior differs under the declared Verilator zero policies and Icarus four-state representation.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F14.sv"
    },
    {
      "id": "F15",
      "title": "Case equality against unknown",
      "category": "four-state",
      "source": "harness/hdl-simulator-observations/fixtures/F15.sv",
      "source_sha256": "78927603724403e8b85ea19cf4f23b5635348be2c09e7c30118bea79502c817f",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS ordinary=x case_x=1 unknown=1\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS ordinary=x case_x=1 unknown=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:55.039768+00:00",
          "log": "harness/hdl-simulator-observations/logs/F15-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS ordinary=1 case_x=0 unknown=0\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS ordinary=1 case_x=0 unknown=0"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:01.765707+00:00",
          "log": "harness/hdl-simulator-observations/logs/F15-verilator.json"
        }
      },
      "observed_payload_equal": false,
      "interpretation": "Unknown or initialization behavior differs under the declared Verilator zero policies and Icarus four-state representation.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F15.sv"
    },
    {
      "id": "F16",
      "title": "Reduction with unknown bit",
      "category": "four-state",
      "source": "harness/hdl-simulator-observations/fixtures/F16.sv",
      "source_sha256": "87ffe117fc76c21bc10abdcec046cec858d15aa19b26431be4b4b7445d3debd3",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS and=x or=1 xor=x\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS and=x or=1 xor=x"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:33:55.181495+00:00",
          "log": "harness/hdl-simulator-observations/logs/F16-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS and=0 or=1 xor=1\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS and=0 or=1 xor=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:01.856809+00:00",
          "log": "harness/hdl-simulator-observations/logs/F16-verilator.json"
        }
      },
      "observed_payload_equal": false,
      "interpretation": "Unknown or initialization behavior differs under the declared Verilator zero policies and Icarus four-state representation.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F16.sv"
    },
    {
      "id": "F17",
      "title": "Controlling bitwise zero",
      "category": "four-state",
      "source": "harness/hdl-simulator-observations/fixtures/F17.sv",
      "source_sha256": "e475976d33161df346eda9841a7d7852efbfeaea566e7d29f079301983cc2bf8",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS x_and_0=0 x_or_1=1\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS x_and_0=0 x_or_1=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:01.803639+00:00",
          "log": "harness/hdl-simulator-observations/logs/F17-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS x_and_0=0 x_or_1=1\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS x_and_0=0 x_or_1=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:08.258192+00:00",
          "log": "harness/hdl-simulator-observations/logs/F17-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F17.sv"
    },
    {
      "id": "F18",
      "title": "Unknown XOR operand",
      "category": "four-state",
      "source": "harness/hdl-simulator-observations/fixtures/F18.sv",
      "source_sha256": "5d83673ab342a8318fc02d2412afe3f5abbbfbdd601fbab4a05bddda8f2768a5",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS x_xor_0=x\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS x_xor_0=x"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:01.894927+00:00",
          "log": "harness/hdl-simulator-observations/logs/F18-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS x_xor_0=0\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS x_xor_0=0"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:08.352554+00:00",
          "log": "harness/hdl-simulator-observations/logs/F18-verilator.json"
        }
      },
      "observed_payload_equal": false,
      "interpretation": "Unknown or initialization behavior differs under the declared Verilator zero policies and Icarus four-state representation.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F18.sv"
    },
    {
      "id": "F19",
      "title": "Two-state bit assignment",
      "category": "four-state",
      "source": "harness/hdl-simulator-observations/fixtures/F19.sv",
      "source_sha256": "2d48bdf32bd532b6413427d2360bac6099c56403b28de17b415a1b76f46cba35",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS bit=0 logic=x\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS bit=0 logic=x"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:08.296197+00:00",
          "log": "harness/hdl-simulator-observations/logs/F19-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS bit=0 logic=0\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS bit=0 logic=0"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:14.825460+00:00",
          "log": "harness/hdl-simulator-observations/logs/F19-verilator.json"
        }
      },
      "observed_payload_equal": false,
      "interpretation": "Unknown or initialization behavior differs under the declared Verilator zero policies and Icarus four-state representation.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F19.sv"
    },
    {
      "id": "F20",
      "title": "Explicit register initialization",
      "category": "initialization",
      "source": "harness/hdl-simulator-observations/fixtures/F20.sv",
      "source_sha256": "a07aae4ba39a68e4d8853e70d1758a1b6676e0e4250737f414c3e49c42438279",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS value=5a\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS value=5a"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:08.386765+00:00",
          "log": "harness/hdl-simulator-observations/logs/F20-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS value=5a\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS value=5a"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:14.904042+00:00",
          "log": "harness/hdl-simulator-observations/logs/F20-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F20.sv"
    },
    {
      "id": "F21",
      "title": "Declaration initialization",
      "category": "initialization",
      "source": "harness/hdl-simulator-observations/fixtures/F21.sv",
      "source_sha256": "e72bd55204fd0927ced653f4dfeae5a8e9b5bd81375040abf2497ce913e1298f",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS value=a5\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS value=a5"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:14.861956+00:00",
          "log": "harness/hdl-simulator-observations/logs/F21-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS value=a5\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS value=a5"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:21.979088+00:00",
          "log": "harness/hdl-simulator-observations/logs/F21-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F21.sv"
    },
    {
      "id": "F22",
      "title": "Blocking statements in one process",
      "category": "ordering",
      "source": "harness/hdl-simulator-observations/fixtures/F22.sv",
      "source_sha256": "03c3754609871e44d06bc60435cd77246f75670e36b1b8bf4d40f5357ab2bec9",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS a=2 b=2\nfixture.sv:7: $finish called at 1000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=2 b=2"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:14.948105+00:00",
          "log": "harness/hdl-simulator-observations/logs/F22-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS a=2 b=2\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=2 b=2"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:22.050492+00:00",
          "log": "harness/hdl-simulator-observations/logs/F22-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F22.sv"
    },
    {
      "id": "F23",
      "title": "Nonblocking swap after edge",
      "category": "ordering",
      "source": "harness/hdl-simulator-observations/fixtures/F23.sv",
      "source_sha256": "ac5e085093e19074477c2675d4340505f30c5c9637dce88f70f6f67144ab7055",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS a=2 b=1\nfixture.sv:8: $finish called at 6000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=2 b=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:22.020930+00:00",
          "log": "harness/hdl-simulator-observations/logs/F23-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS a=2 b=1\n- fixture.sv:8: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=2 b=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:28.780946+00:00",
          "log": "harness/hdl-simulator-observations/logs/F23-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F23.sv"
    },
    {
      "id": "F24",
      "title": "Last nonblocking assignment in process",
      "category": "ordering",
      "source": "harness/hdl-simulator-observations/fixtures/F24.sv",
      "source_sha256": "a6b86428c170c71e11c15105544b8a93477e8d9f256abbfe4e224aab0cf5233f",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS a=2\nfixture.sv:8: $finish called at 6000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=2"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:22.089038+00:00",
          "log": "harness/hdl-simulator-observations/logs/F24-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS a=2\n- fixture.sv:8: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=2"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:28.982057+00:00",
          "log": "harness/hdl-simulator-observations/logs/F24-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F24.sv"
    },
    {
      "id": "F25",
      "title": "Three-stage pipeline",
      "category": "ordering",
      "source": "harness/hdl-simulator-observations/fixtures/F25.sv",
      "source_sha256": "c1021e94d67e5edaacd3c02d6b9b8128d56fe309cb767e07693e15c4bbda14f3",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS a=1 b=0 c=0\nOBS a=2 b=1 c=0\nOBS a=3 b=2 c=1\nfixture.sv:8: $finish called at 30000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=1 b=0 c=0",
            "OBS a=2 b=1 c=0",
            "OBS a=3 b=2 c=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:28.820531+00:00",
          "log": "harness/hdl-simulator-observations/logs/F25-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS a=1 b=0 c=0\nOBS a=2 b=1 c=0\nOBS a=3 b=2 c=1\n- fixture.sv:8: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS a=1 b=0 c=0",
            "OBS a=2 b=1 c=0",
            "OBS a=3 b=2 c=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:35.595079+00:00",
          "log": "harness/hdl-simulator-observations/logs/F25-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F25.sv"
    },
    {
      "id": "F26",
      "title": "Opposite-edge stimulus",
      "category": "ordering",
      "source": "harness/hdl-simulator-observations/fixtures/F26.sv",
      "source_sha256": "347f5ea6289e2505fd39f577011d62971b567703088bb4319143728a1f713388",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS d=1 q=1\nfixture.sv:9: $finish called at 16000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS d=1 q=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:29.020620+00:00",
          "log": "harness/hdl-simulator-observations/logs/F26-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS d=1 q=1\n- fixture.sv:9: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS d=1 q=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:35.867616+00:00",
          "log": "harness/hdl-simulator-observations/logs/F26-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F26.sv"
    },
    {
      "id": "F27",
      "title": "Asynchronous reset then clock",
      "category": "initialization",
      "source": "harness/hdl-simulator-observations/fixtures/F27.sv",
      "source_sha256": "0a67367fb1e012f52b0017c00b810605f9702f89def4b50e9abef78e9aad0881",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS reset_q=0\nOBS clock_q=1\nfixture.sv:8: $finish called at 6000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS reset_q=0",
            "OBS clock_q=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:35.636914+00:00",
          "log": "harness/hdl-simulator-observations/logs/F27-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS reset_q=0\nOBS clock_q=1\n- fixture.sv:8: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS reset_q=0",
            "OBS clock_q=1"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:42.172968+00:00",
          "log": "harness/hdl-simulator-observations/logs/F27-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F27.sv"
    },
    {
      "id": "F28",
      "title": "Explicit modulo arithmetic sequence",
      "category": "seed",
      "source": "harness/hdl-simulator-observations/fixtures/F28.sv",
      "source_sha256": "f4a2d780509909502456575bd2c896a6702351ac19867a85ab9f3091eeaf6d46",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS state=3d20bdba\nOBS state=e9dab1d1\nOBS state=9ccc40fc\nfixture.sv:7: $finish called at 3000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS state=3d20bdba",
            "OBS state=e9dab1d1",
            "OBS state=9ccc40fc"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:35.905720+00:00",
          "log": "harness/hdl-simulator-observations/logs/F28-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS state=3d20bdba\nOBS state=e9dab1d1\nOBS state=9ccc40fc\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS state=3d20bdba",
            "OBS state=e9dab1d1",
            "OBS state=9ccc40fc"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:42.405847+00:00",
          "log": "harness/hdl-simulator-observations/logs/F28-verilator.json"
        }
      },
      "observed_payload_equal": true,
      "interpretation": "Matching OBS payload in these configurations; finish banners and diagnostics are compared separately.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F28.sv"
    },
    {
      "id": "F29",
      "title": "Seeded random sequence",
      "category": "seed",
      "source": "harness/hdl-simulator-observations/fixtures/F29.sv",
      "source_sha256": "11fead1264b002b05f40b694ae402d01b82e6573251ff1cef3b7924d546bb38e",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS random=8011ec00 seed=0011ea9e\nOBS random=61e0e9c3 seed=e1e0e687\nOBS random=b3547666 seed=3354751c\nfixture.sv:7: $finish called at 3000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS random=8011ec00 seed=0011ea9e",
            "OBS random=61e0e9c3 seed=e1e0e687",
            "OBS random=b3547666 seed=3354751c"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:42.215338+00:00",
          "log": "harness/hdl-simulator-observations/logs/F29-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS random=979a27f1 seed=a79f332a\nOBS random=7d04cbad seed=83d6c4a7\nOBS random=9c22637a seed=0e23cf8b\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS random=979a27f1 seed=a79f332a",
            "OBS random=7d04cbad seed=83d6c4a7",
            "OBS random=9c22637a seed=0e23cf8b"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:50.365047+00:00",
          "log": "harness/hdl-simulator-observations/logs/F29-verilator.json"
        }
      },
      "observed_payload_equal": false,
      "interpretation": "Built-in seeded random streams differ by implementation; each recorded stream repeats within its own tool.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F29.sv"
    },
    {
      "id": "F30",
      "title": "Seeded urandom process",
      "category": "seed",
      "source": "harness/hdl-simulator-observations/fixtures/F30.sv",
      "source_sha256": "6bb48337f0d4c3ce55ae59da60f175a97f690e5f8b320ef755b5bd72b66d03f3",
      "origin": "Original fixture authored for P6.",
      "observations": {
        "icarus": {
          "tool_version": "13.0 stable v13_0",
          "compile_command": [
            "iverilog",
            "-B",
            "${ICARUS_LIB}",
            "-g2012",
            "-gstrict-expr-width",
            "-Wall",
            "-s",
            "tb",
            "-o",
            "run.vvp",
            "fixture.sv"
          ],
          "execute_command": [
            "vvp",
            "-M",
            "${ICARUS_LIB}",
            "run.vvp"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS urandom=0011ec00\nOBS urandom=e1e0e9c3\nOBS urandom=33547666\nfixture.sv:7: $finish called at 3000 (1ps)\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS urandom=0011ec00",
            "OBS urandom=e1e0e9c3",
            "OBS urandom=33547666"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:42.450798+00:00",
          "log": "harness/hdl-simulator-observations/logs/F30-icarus.json"
        },
        "verilator": {
          "tool_version": "5.052 2026-09-05 rev vUNKNOWN-built20260905",
          "compile_command": [
            "verilator",
            "--binary",
            "--timing",
            "--language",
            "1800-2012",
            "--x-assign",
            "0",
            "--x-initial",
            "0",
            "-Wno-fatal",
            "--quiet-build",
            "--quiet-stats",
            "--quiet-exit",
            "--top-module",
            "tb",
            "--Mdir",
            "obj",
            "fixture.sv"
          ],
          "execute_command": [
            "./obj/Vtb",
            "+verilator+quiet"
          ],
          "compile_return_code": 0,
          "execute_return_code": 0,
          "compile_stdout": "",
          "compile_stderr": "",
          "runtime_stdout": "OBS urandom=a79f332a\nOBS urandom=979a27f1\nOBS urandom=b38d6fdb\n- fixture.sv:7: Verilog $finish\n",
          "runtime_stderr": "",
          "observed_lines": [
            "OBS urandom=a79f332a",
            "OBS urandom=979a27f1",
            "OBS urandom=b38d6fdb"
          ],
          "repeat_observed_lines_equal": true,
          "recorded_at_utc": "2026-10-25T02:34:50.602193+00:00",
          "log": "harness/hdl-simulator-observations/logs/F30-verilator.json"
        }
      },
      "observed_payload_equal": false,
      "interpretation": "Built-in seeded random streams differ by implementation; each recorded stream repeats within its own tool.",
      "public_source_path": "/data/hdl-simulator-observations/fixtures/F30.sv"
    }
  ],
  "limits": [
    "Thirty small examples are not a language-compliance suite or a tool ranking.",
    "No analog metastability, silicon timing, power intent, physical implementation or performance measurement.",
    "Verilator zero X policies are selected settings, not every supported mode.",
    "Only original fixture sources, logs and reproduction code are included; installed tools and generated binaries are excluded."
  ]
}
