{
  "page_id": "P03",
  "recorded_at_utc": "2026-10-25T14:31:09.376588+00:00",
  "tools": [
    {
      "name": "Verilator",
      "version": "5.052",
      "source_commit": "ea338be98e1e838d3518809ce8899f85a009963c",
      "source_url": "https://github.com/verilator/verilator/tree/ea338be98e1e838d3518809ce8899f85a009963c"
    }
  ],
  "os": "macOS 27.0.1",
  "architecture": "arm64",
  "input_sha256": "6590ec1cf093b34c90062f6edc70383ff0116d73ae6426732a2d1bb85c01d6aa",
  "coverage_scope": "Verilator line and branch coverage of the configured bounded_adder only; testbench explicitly excluded. Functional counters and checker are original SystemVerilog output. No toggle, expression or FSM percentage claimed.",
  "cases": [
    {
      "command": [
        "${VERILATOR}/bin/verilator",
        "--binary",
        "--timing",
        "--coverage-line",
        "--top-module",
        "tb",
        "-GFIX=0",
        "-Wno-fatal",
        "--quiet-build",
        "--quiet-stats",
        "--quiet-exit",
        "--Mdir",
        "obj0",
        "example.sv"
      ],
      "started_at_utc": "2026-10-25T14:31:00.640944+00:00",
      "ended_at_utc": "2026-10-25T14:31:04.763608+00:00",
      "return_code": 0,
      "stdout": "",
      "stderr": "%Warning-WIDTHTRUNC: example.sv:53:5: Logical operator IF expects 1 bit on the If, but If's VARREF 'extended' generates 32 bits.\n                                    : ... note: In instance 'tb'\n   53 |     if (extended) sample(1, 3, 1);\n      |     ^~\n                     ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.052\n                     ... Use \"/* verilator lint_off WIDTHTRUNC */\" and lint_on around source to disable this message.\n",
      "case": "compile_fix_0"
    },
    {
      "command": [
        "${TEMP}/chip-e1-simulations/obj0/Vtb",
        "+extended=0",
        "+verilator+coverage+file+${TEMP}/chip-e1-simulations/fix0_extended0.dat",
        "+verilator+quiet"
      ],
      "started_at_utc": "2026-10-25T14:31:04.769576+00:00",
      "ended_at_utc": "2026-10-25T14:31:04.883374+00:00",
      "return_code": 0,
      "stdout": "enable=0 a=1 b=1 expected=0 result=0\nenable=1 a=1 b=1 expected=2 result=2\nFUNCTIONAL disabled=1 ordinary=1 overflow=0\nCHECKER mismatches=0\n- example.sv:57: Verilog $finish\n",
      "stderr": "",
      "case": "fix0_extended0"
    },
    {
      "command": [
        "${VERILATOR}/bin/verilator_coverage_bin_dbg",
        "--annotate",
        "${TEMP}/chip-e1-simulations/fix0_extended0-annotated",
        "--annotate-min",
        "1",
        "${TEMP}/chip-e1-simulations/fix0_extended0.dat"
      ],
      "started_at_utc": "2026-10-25T14:31:04.883412+00:00",
      "ended_at_utc": "2026-10-25T14:31:04.987950+00:00",
      "return_code": 0,
      "stdout": "Coverage Summary:\n  line      : 100.0% (1/1)\n  toggle    : 0.0% (0/0)\n  branch    : 100.0% (2/2)\n  expr      : 0.0% (0/0)\n  fsm_state : 0.0% (0/0)\n  fsm_arc   : 0.0% (0/0)\nAnnotation Summary:\n  lines with all attached points covered : 100.00%  (4/4)\n",
      "stderr": "",
      "case": "fix0_extended0_coverage"
    },
    {
      "command": [
        "${TEMP}/chip-e1-simulations/obj0/Vtb",
        "+extended=1",
        "+verilator+coverage+file+${TEMP}/chip-e1-simulations/fix0_extended1.dat",
        "+verilator+quiet"
      ],
      "started_at_utc": "2026-10-25T14:31:05.005264+00:00",
      "ended_at_utc": "2026-10-25T14:31:05.011246+00:00",
      "return_code": 0,
      "stdout": "enable=0 a=1 b=1 expected=0 result=0\nenable=1 a=1 b=1 expected=2 result=2\nenable=1 a=3 b=1 expected=3 result=0\nFUNCTIONAL disabled=1 ordinary=1 overflow=1\nCHECKER mismatches=1\n- example.sv:57: Verilog $finish\n",
      "stderr": "",
      "case": "fix0_extended1"
    },
    {
      "command": [
        "${VERILATOR}/bin/verilator_coverage_bin_dbg",
        "--annotate",
        "${TEMP}/chip-e1-simulations/fix0_extended1-annotated",
        "--annotate-min",
        "1",
        "${TEMP}/chip-e1-simulations/fix0_extended1.dat"
      ],
      "started_at_utc": "2026-10-25T14:31:05.011298+00:00",
      "ended_at_utc": "2026-10-25T14:31:05.016068+00:00",
      "return_code": 0,
      "stdout": "Coverage Summary:\n  line      : 100.0% (1/1)\n  toggle    : 0.0% (0/0)\n  branch    : 100.0% (2/2)\n  expr      : 0.0% (0/0)\n  fsm_state : 0.0% (0/0)\n  fsm_arc   : 0.0% (0/0)\nAnnotation Summary:\n  lines with all attached points covered : 100.00%  (4/4)\n",
      "stderr": "",
      "case": "fix0_extended1_coverage"
    },
    {
      "command": [
        "${VERILATOR}/bin/verilator",
        "--binary",
        "--timing",
        "--coverage-line",
        "--top-module",
        "tb",
        "-GFIX=1",
        "-Wno-fatal",
        "--quiet-build",
        "--quiet-stats",
        "--quiet-exit",
        "--Mdir",
        "obj1",
        "example.sv"
      ],
      "started_at_utc": "2026-10-25T14:31:05.034673+00:00",
      "ended_at_utc": "2026-10-25T14:31:09.204582+00:00",
      "return_code": 0,
      "stdout": "",
      "stderr": "%Warning-WIDTHTRUNC: example.sv:53:5: Logical operator IF expects 1 bit on the If, but If's VARREF 'extended' generates 32 bits.\n                                    : ... note: In instance 'tb'\n   53 |     if (extended) sample(1, 3, 1);\n      |     ^~\n                     ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.052\n                     ... Use \"/* verilator lint_off WIDTHTRUNC */\" and lint_on around source to disable this message.\n",
      "case": "compile_fix_1"
    },
    {
      "command": [
        "${TEMP}/chip-e1-simulations/obj1/Vtb",
        "+extended=1",
        "+verilator+coverage+file+${TEMP}/chip-e1-simulations/fix1_extended1.dat",
        "+verilator+quiet"
      ],
      "started_at_utc": "2026-10-25T14:31:09.210542+00:00",
      "ended_at_utc": "2026-10-25T14:31:09.370411+00:00",
      "return_code": 0,
      "stdout": "enable=0 a=1 b=1 expected=0 result=0\nenable=1 a=1 b=1 expected=2 result=2\nenable=1 a=3 b=1 expected=3 result=3\nFUNCTIONAL disabled=1 ordinary=1 overflow=1\nCHECKER mismatches=0\n- example.sv:57: Verilog $finish\n",
      "stderr": "",
      "case": "fix1_extended1"
    },
    {
      "command": [
        "${VERILATOR}/bin/verilator_coverage_bin_dbg",
        "--annotate",
        "${TEMP}/chip-e1-simulations/fix1_extended1-annotated",
        "--annotate-min",
        "1",
        "${TEMP}/chip-e1-simulations/fix1_extended1.dat"
      ],
      "started_at_utc": "2026-10-25T14:31:09.370458+00:00",
      "ended_at_utc": "2026-10-25T14:31:09.375412+00:00",
      "return_code": 0,
      "stdout": "Coverage Summary:\n  line      : 100.0% (4/4)\n  toggle    : 0.0% (0/0)\n  branch    : 0.0% (0/0)\n  expr      : 0.0% (0/0)\n  fsm_state : 0.0% (0/0)\n  fsm_arc   : 0.0% (0/0)\nAnnotation Summary:\n  lines with all attached points covered : 100.00%  (5/5)\n",
      "stderr": "",
      "case": "fix1_extended1_coverage"
    }
  ],
  "publication_omissions": "Routine elapsed-time and allocation summaries omitted; behavior and diagnostics retained, absolute installation/build paths use portable tokens.",
  "observed_runtime_provenance": {
    "observed_version": "Verilator 5.052 2026-09-05 rev vUNKNOWN-built20260905",
    "binary_sha256": "097580ddc591fb42c09e0c72757e341cd740a55ccad8c50cf4b0d39f6c92dac4",
    "version_source_commit_basis": "Pinned official v5.052 source commit; binary reports vUNKNOWN-built20260905 and is not independently attested to that commit."
  },
  "earlier_record": "data/measurements/printed-hdl/earlier-p8/P03-verilator.json",
  "summary_tool": {
    "name": "verilator_coverage_bin_dbg",
    "version": "5.052",
    "sha256": "8c3d3c473f53b32eb3e1c535cd29cdefa6a63fde7c829993a5995669e3f30ddb",
    "scope": "Annotation summaries at minimum one hit; the driver named verilator_coverage was not used for these summaries."
  }
}