{
  "page_id": "P14",
  "tool": {
    "version": "5.052",
    "source_commit": "ea338be98e1e838d3518809ce8899f85a009963c",
    "source_url": "https://github.com/verilator/verilator/tree/v5.052",
    "executable_sha256": "097580ddc591fb42c09e0c72757e341cd740a55ccad8c50cf4b0d39f6c92dac4"
  },
  "environment": {
    "os": "macOS 27.0.1",
    "architecture": "arm64",
    "compiler": "Apple clang 21.0.0"
  },
  "source_files": {
    "data/examples/axi-handshake-deadlocks/example.sv": "35f7b03036a344733a331308d5c67bc8f3944eb1fa3d971b85e385c622a9e248"
  },
  "compile": {
    "command": [
      "verilator",
      "--binary",
      "--timing",
      "--assert",
      "--coverage-user",
      "--language",
      "1800-2012",
      "-Wno-fatal",
      "--quiet-build",
      "--quiet-stats",
      "--quiet-exit",
      "--top-module",
      "tb",
      "--Mdir",
      "obj",
      "example.sv"
    ],
    "started_at_utc": "2026-10-25T14:30:53.832319+00:00",
    "ended_at_utc": "2026-10-25T14:30:57.938720+00:00",
    "return_code": 0,
    "stdout": "",
    "stderr": ""
  },
  "cases": [
    {
      "mode": 0,
      "command": [
        "./obj/Vtb",
        "+verilator+quiet",
        "+MODE=0",
        "+verilator+coverage+file+coverage-0.dat"
      ],
      "started_at_utc": "2026-10-25T14:30:57.938748+00:00",
      "ended_at_utc": "2026-10-25T14:30:58.057020+00:00",
      "return_code": 0,
      "stdout": "MODE 0 budget=4 capacity=1\nTRACE cycle=0 pending=1 valid=1 ready=0 id=0 wire_id=0 data=5a\nTRACE cycle=1 pending=1 valid=1 ready=0 id=0 wire_id=0 data=5a\nTRACE cycle=2 pending=1 valid=1 ready=1 id=0 wire_id=0 data=5a\nTRACE cycle=3 pending=0 valid=0 ready=1 id=0 wire_id=0 data=5a\nTRACE cycle=4 pending=0 valid=0 ready=1 id=0 wire_id=0 data=5a\nTRACE cycle=5 pending=0 valid=0 ready=1 id=0 wire_id=0 data=5a\nTRACE cycle=6 pending=0 valid=0 ready=1 id=0 wire_id=0 data=5a\nTRACE cycle=7 pending=0 valid=0 ready=1 id=0 wire_id=0 data=5a\nRESULT transfers=1 bounded_wait=0 id_errors=0 limit_errors=0\n- example.sv:87: Verilog $finish\n",
      "stderr": ""
    },
    {
      "mode": 1,
      "command": [
        "./obj/Vtb",
        "+verilator+quiet",
        "+MODE=1",
        "+verilator+coverage+file+coverage-1.dat"
      ],
      "started_at_utc": "2026-10-25T14:30:58.057049+00:00",
      "ended_at_utc": "2026-10-25T14:30:58.061089+00:00",
      "return_code": 0,
      "stdout": "MODE 1 budget=4 capacity=1\nTRACE cycle=0 pending=1 valid=0 ready=0 id=0 wire_id=0 data=5a\nTRACE cycle=1 pending=1 valid=0 ready=0 id=0 wire_id=0 data=5a\nTRACE cycle=2 pending=1 valid=0 ready=0 id=0 wire_id=0 data=5a\nTRACE cycle=3 pending=1 valid=0 ready=0 id=0 wire_id=0 data=5a\nBOUNDED_WAIT cycle=3 waited=4\nTRACE cycle=4 pending=1 valid=0 ready=0 id=0 wire_id=0 data=5a\nTRACE cycle=5 pending=1 valid=0 ready=0 id=0 wire_id=0 data=5a\nTRACE cycle=6 pending=1 valid=0 ready=0 id=0 wire_id=0 data=5a\nTRACE cycle=7 pending=1 valid=0 ready=0 id=0 wire_id=0 data=5a\nRESULT transfers=0 bounded_wait=1 id_errors=0 limit_errors=0\n- example.sv:87: Verilog $finish\n",
      "stderr": ""
    },
    {
      "mode": 2,
      "command": [
        "./obj/Vtb",
        "+verilator+quiet",
        "+MODE=2",
        "+verilator+coverage+file+coverage-2.dat"
      ],
      "started_at_utc": "2026-10-25T14:30:58.061114+00:00",
      "ended_at_utc": "2026-10-25T14:30:58.064819+00:00",
      "return_code": 0,
      "stdout": "MODE 2 budget=4 capacity=1\nTRACE cycle=0 pending=1 valid=1 ready=0 id=2 wire_id=0 data=5a\nTRACE cycle=1 pending=1 valid=1 ready=0 id=2 wire_id=0 data=5a\nTRACE cycle=2 pending=1 valid=1 ready=1 id=2 wire_id=0 data=5a\nID_MISMATCH sent=2 received=0\nTRACE cycle=3 pending=0 valid=0 ready=1 id=2 wire_id=0 data=5a\nTRACE cycle=4 pending=0 valid=0 ready=1 id=2 wire_id=0 data=5a\nTRACE cycle=5 pending=0 valid=0 ready=1 id=2 wire_id=0 data=5a\nTRACE cycle=6 pending=0 valid=0 ready=1 id=2 wire_id=0 data=5a\nTRACE cycle=7 pending=0 valid=0 ready=1 id=2 wire_id=0 data=5a\nRESULT transfers=1 bounded_wait=0 id_errors=1 limit_errors=0\n- example.sv:87: Verilog $finish\n",
      "stderr": ""
    },
    {
      "mode": 3,
      "command": [
        "./obj/Vtb",
        "+verilator+quiet",
        "+MODE=3",
        "+verilator+coverage+file+coverage-3.dat"
      ],
      "started_at_utc": "2026-10-25T14:30:58.064839+00:00",
      "ended_at_utc": "2026-10-25T14:30:58.068286+00:00",
      "return_code": 0,
      "stdout": "MODE 3 budget=4 capacity=1\nTRACE cycle=0 pending=1 valid=1 ready=0 id=0 wire_id=0 data=5a\nTRACE cycle=1 pending=1 valid=1 ready=0 id=0 wire_id=0 data=5a\nTRACE cycle=2 pending=1 valid=1 ready=1 id=0 wire_id=0 data=5a\nTRACE cycle=3 pending=1 valid=1 ready=1 id=1 wire_id=1 data=5a\nOUTSTANDING_LIMIT count=2\nTRACE cycle=4 pending=0 valid=0 ready=1 id=1 wire_id=1 data=5a\nTRACE cycle=5 pending=0 valid=0 ready=1 id=1 wire_id=1 data=5a\nTRACE cycle=6 pending=0 valid=0 ready=1 id=1 wire_id=1 data=5a\nTRACE cycle=7 pending=0 valid=0 ready=1 id=1 wire_id=1 data=5a\nRESULT transfers=2 bounded_wait=0 id_errors=0 limit_errors=1\n- example.sv:87: Verilog $finish\n",
      "stderr": ""
    }
  ],
  "redaction": "Only environment paths are replaced with tokens; diagnostics otherwise retain literal text.",
  "earlier_record": "data/measurements/printed-hdl/earlier-p8/P14-verilator.json",
  "publication_omissions": "Routine elapsed-time and allocation summaries omitted; behavior and diagnostics retained, absolute installation/build paths use portable tokens."
}