{ "page_id": "P15", "recorded_at_utc": "2026-10-25T14:29:51.884181+00:00", "provenance": { "tool": "Yosys", "version": "0.70+post", "release_tag": "v0.70", "release_tag_commit": "28ba3cb926fe376fa05ebfc1b921747d011d4557", "release_tag_url": "https://github.com/YosysHQ/yosys/releases/tag/v0.70", "binary_reported_revision": "0c11ea098be065e585a90a06e7b7da49936cf231", "binary_version_output": "Yosys 0.70+post (git sha1 0c11ea098be065e585a90a06e7b7da49936cf231, Release, AppleClang clang++ 21.0.0.21000334)", "binary_sha256": "aff1882664d6775739a1d99d086e054dc71ca6d22d2a6d0d3ee6f3e382fa0daf", "revision_note": "The binary reports 0.70+post and the revision above. That revision is not the official v0.70 tag commit. The binary source build was not independently reconstructed.", "os": "macOS 27.0.1", "architecture": "arm64" }, "cases": [ { "case": "bounded_5", "started_at_utc": "2026-10-25T14:29:51.782948+00:00", "ended_at_utc": "2026-10-25T14:29:51.792635+00:00", "command": [ "${TOOL_WORKSPACE}/runtime/formal-tools/cellar/yosys/0.70/bin/yosys", "-Q", "-T", "-s", "bounded_5.ys" ], "return_code": 0, "stdout": "\n-- Executing script file `bounded_5.ys' --\n\n1. Executing Verilog-2005 frontend: late_bug.sv\nParsing formal SystemVerilog input from `late_bug.sv' to AST representation.\nGenerating RTLIL representation for module `\\late_bug'.\nSuccessfully finished Verilog frontend.\n\n2. Executing PREP pass.\n\n2.1. Executing HIERARCHY pass (managing design hierarchy).\n\n2.1.1. Analyzing design hierarchy..\nTop module: \\late_bug\n\n2.1.2. Analyzing design hierarchy..\nTop module: \\late_bug\nRemoved 0 unused modules.\n\n2.2. Executing PROC pass (convert processes to netlists).\n\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nCleaned up 0 empty switches.\n\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nRemoved a total of 0 dead cases.\n\n2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 0 redundant assignments.\nPromoted 2 assignments to connections.\n\n2.2.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\late_bug.$proc$late_bug.sv:3$4'.\n Set init value: \\cycles = 3'000\n\n2.2.5. Executing PROC_ARST pass (detect async resets in processes).\n\n2.2.6. Executing PROC_ROM pass (convert switches to ROMs).\nConverted 0 switches.\n\n2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\late_bug.$proc$late_bug.sv:3$4'.\nCreating decoders for process `\\late_bug.$proc$late_bug.sv:4$1'.\n\n2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).\n\n2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\late_bug.\\cycles' using process `\\late_bug.$proc$late_bug.sv:4$1'.\n created $dff cell `$procdff$5' with positive edge clock.\n\n2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).\n\n2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `late_bug.$proc$late_bug.sv:3$4'.\nRemoving empty process `late_bug.$proc$late_bug.sv:4$1'.\nCleaned up 0 empty switches.\n\n2.2.12. Executing OPT_EXPR pass (perform const folding).\nOptimizing module late_bug.\n\n2.3. Executing FUTURE pass.\n\n2.4. Executing OPT_EXPR pass (perform const folding).\nOptimizing module late_bug.\n\n2.5. Executing CHECK pass (checking for obvious problems).\nChecking module late_bug...\nFound and reported 0 problems.\n\n2.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\late_bug..\nRemoved 0 unused cells and 3 unused wires.\n\n\n2.7. Executing OPT pass (performing simple optimizations).\n\n2.7.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module late_bug.\n\n2.7.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\late_bug'.\nComputing hashes of 3 cells of `\\late_bug'.\nFinding duplicate cells in `\\late_bug'.\nRemoved a total of 0 cells.\n\n2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\late_bug..\n Creating internal representation of mux trees.\n No muxes found in this module.\nRemoved 0 multiplexer ports.\n\n2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\late_bug.\nPerformed a total of 0 changes.\n\n2.7.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\late_bug'.\nComputing hashes of 3 cells of `\\late_bug'.\nFinding duplicate cells in `\\late_bug'.\nRemoved a total of 0 cells.\n\n2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\late_bug..\n\n2.7.7. Executing OPT_EXPR pass (perform const folding).\nOptimizing module late_bug.\n\n2.7.8. Finished fast OPT passes. (There is nothing left to do.)\n\n2.8. Executing WREDUCE pass (reducing word size of cells).\n\n2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\late_bug..\n\n2.10. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n2.11. Executing OPT pass (performing simple optimizations).\n\n2.11.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module late_bug.\n\n2.11.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\late_bug'.\nComputing hashes of 3 cells of `\\late_bug'.\nFinding duplicate cells in `\\late_bug'.\nRemoved a total of 0 cells.\n\n2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\late_bug..\n\n2.11.4. Finished fast OPT passes.\n\n2.12. Executing SORT pass.\n\n2.13. Printing statistics.\n\n=== late_bug ===\n\n +----------Local Count, excluding submodules.\n | \n 5 wires\n 11 wire bits\n 4 public wires\n 8 public wire bits\n 3 ports\n 5 port bits\n 3 cells\n 1 $add\n 1 $dff\n 1 $eq\n\n2.14. Executing CHECK pass (checking for obvious problems).\nChecking module late_bug...\nFound and reported 0 problems.\n\n3. Executing SAT pass (solving SAT problems in the circuit).\nUsing SAT solver `minisat`.\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 3 cells to SAT database.\nImport set-constraint from init attribute: \\cycles = 3'000\nFinal init constraint equation: \\cycles = 3'000\nImport proof-constraint: \\bad = 1'0\nFinal proof equation: \\bad = 1'0\n\nSetting up time step 2:\nFinal constraint equation: { } = { }\nImported 3 cells to SAT database.\nImport proof-constraint: \\bad = 1'0\nFinal proof equation: \\bad = 1'0\n\nSetting up time step 3:\nFinal constraint equation: { } = { }\nImported 3 cells to SAT database.\nImport proof-constraint: \\bad = 1'0\nFinal proof equation: \\bad = 1'0\n\nSetting up time step 4:\nFinal constraint equation: { } = { }\nImported 3 cells to SAT database.\nImport proof-constraint: \\bad = 1'0\nFinal proof equation: \\bad = 1'0\n\nSetting up time step 5:\nFinal constraint equation: { } = { }\nImported 3 cells to SAT database.\nImport proof-constraint: \\bad = 1'0\nFinal proof equation: \\bad = 1'0\nImport show expression: \\clk\nImport show expression: \\bad\nImport show expression: \\count\n\nSolving problem with 228 variables and 609 clauses..\nSAT proof finished - no model found: SUCCESS!\n\n /$$$$$$ /$$$$$$$$ /$$$$$$$ \n /$$__ $$ | $$_____/ | $$__ $$ \n | $$ \\ $$ | $$ | $$ \\ $$ \n | $$ | $$ | $$$$$ | $$ | $$ \n | $$ | $$ | $$__/ | $$ | $$ \n | $$/$$ $$ | $$ | $$ | $$ \n | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$\n \\____ $$$|__/|________/|__/|_______/|__/\n \\__/ \n\n", "stderr": "", "input_sha256": { "masked_bounded.ys": "bdf178d6f6c134c23ec056dfe99ad2095ba2b620a1f6f3b3034bd279a5688164", "strengthened_induction.ys": "c0f9849e3ed933ca38ff6a961adbbb08017f360266a684d29f70f61a6d627d11", "induction.sv": "31bfa2953dcfa67a352feb3bee5def35e0944c46caaf00326ee1a8dca4e486e6", "weak_induction.ys": "0c9564190e299dda044a38efa0dd59261d8f72b68d79147caf1e1cf04af960e2", "bounded_5.ys": "827a75335345d035df12c9d3ab0d1b06fcf6c79361bd3de5a7e64ad84cf7869d", "cover_unmasked.ys": "bcfcf94773673c7dde5237346acbcf416a5fa1821a308554c66b5dc9317de9a4", "deeper_6.ys": "b3e328858b39a400de7ebdff4170fb85843cb5746f307c628b8df66d4727a764", "masked_bug.sv": "44c0ab027ad89a94a5856227adcf4d4d01dffce43e634c8840fe68b31b3818c7", "cover_masked.ys": "7a78e789233cb208939ecb7267ac42a099e427c6179700ac6278774556a34bf9", "weak_induction_depth2.ys": "8b71caad233b5b514ba990032c06b6f7afdd0a042a76d484b660026554f56cfd", "late_bug.sv": "b2e71f3b573a9e6fb45ea383dca35c786c8c95492c84af8ed89a119acd8b2365" } }, { "case": "deeper_6", "started_at_utc": "2026-10-25T14:29:51.795046+00:00", "ended_at_utc": "2026-10-25T14:29:51.805255+00:00", "command": [ "${TOOL_WORKSPACE}/runtime/formal-tools/cellar/yosys/0.70/bin/yosys", "-Q", "-T", "-s", "deeper_6.ys" ], "return_code": 0, "stdout": "\n-- Executing script file `deeper_6.ys' --\n\n1. Executing Verilog-2005 frontend: late_bug.sv\nParsing formal SystemVerilog input from `late_bug.sv' to AST representation.\nGenerating RTLIL representation for module `\\late_bug'.\nSuccessfully finished Verilog frontend.\n\n2. Executing PREP pass.\n\n2.1. Executing HIERARCHY pass (managing design hierarchy).\n\n2.1.1. Analyzing design hierarchy..\nTop module: \\late_bug\n\n2.1.2. Analyzing design hierarchy..\nTop module: \\late_bug\nRemoved 0 unused modules.\n\n2.2. Executing PROC pass (convert processes to netlists).\n\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nCleaned up 0 empty switches.\n\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nRemoved a total of 0 dead cases.\n\n2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 0 redundant assignments.\nPromoted 2 assignments to connections.\n\n2.2.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\late_bug.$proc$late_bug.sv:3$4'.\n Set init value: \\cycles = 3'000\n\n2.2.5. Executing PROC_ARST pass (detect async resets in processes).\n\n2.2.6. Executing PROC_ROM pass (convert switches to ROMs).\nConverted 0 switches.\n\n2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\late_bug.$proc$late_bug.sv:3$4'.\nCreating decoders for process `\\late_bug.$proc$late_bug.sv:4$1'.\n\n2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).\n\n2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\late_bug.\\cycles' using process `\\late_bug.$proc$late_bug.sv:4$1'.\n created $dff cell `$procdff$5' with positive edge clock.\n\n2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).\n\n2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `late_bug.$proc$late_bug.sv:3$4'.\nRemoving empty process `late_bug.$proc$late_bug.sv:4$1'.\nCleaned up 0 empty switches.\n\n2.2.12. Executing OPT_EXPR pass (perform const folding).\nOptimizing module late_bug.\n\n2.3. Executing FUTURE pass.\n\n2.4. Executing OPT_EXPR pass (perform const folding).\nOptimizing module late_bug.\n\n2.5. Executing CHECK pass (checking for obvious problems).\nChecking module late_bug...\nFound and reported 0 problems.\n\n2.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\late_bug..\nRemoved 0 unused cells and 3 unused wires.\n\n\n2.7. Executing OPT pass (performing simple optimizations).\n\n2.7.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module late_bug.\n\n2.7.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\late_bug'.\nComputing hashes of 3 cells of `\\late_bug'.\nFinding duplicate cells in `\\late_bug'.\nRemoved a total of 0 cells.\n\n2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\late_bug..\n Creating internal representation of mux trees.\n No muxes found in this module.\nRemoved 0 multiplexer ports.\n\n2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\late_bug.\nPerformed a total of 0 changes.\n\n2.7.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\late_bug'.\nComputing hashes of 3 cells of `\\late_bug'.\nFinding duplicate cells in `\\late_bug'.\nRemoved a total of 0 cells.\n\n2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\late_bug..\n\n2.7.7. Executing OPT_EXPR pass (perform const folding).\nOptimizing module late_bug.\n\n2.7.8. Finished fast OPT passes. (There is nothing left to do.)\n\n2.8. Executing WREDUCE pass (reducing word size of cells).\n\n2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\late_bug..\n\n2.10. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n2.11. Executing OPT pass (performing simple optimizations).\n\n2.11.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module late_bug.\n\n2.11.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\late_bug'.\nComputing hashes of 3 cells of `\\late_bug'.\nFinding duplicate cells in `\\late_bug'.\nRemoved a total of 0 cells.\n\n2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\late_bug..\n\n2.11.4. Finished fast OPT passes.\n\n2.12. Executing SORT pass.\n\n2.13. Printing statistics.\n\n=== late_bug ===\n\n +----------Local Count, excluding submodules.\n | \n 5 wires\n 11 wire bits\n 4 public wires\n 8 public wire bits\n 3 ports\n 5 port bits\n 3 cells\n 1 $add\n 1 $dff\n 1 $eq\n\n2.14. Executing CHECK pass (checking for obvious problems).\nChecking module late_bug...\nFound and reported 0 problems.\n\n3. Executing SAT pass (solving SAT problems in the circuit).\nUsing SAT solver `minisat`.\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 3 cells to SAT database.\nImport set-constraint from init attribute: \\cycles = 3'000\nFinal init constraint equation: \\cycles = 3'000\nImport proof-constraint: \\bad = 1'0\nFinal proof equation: \\bad = 1'0\n\nSetting up time step 2:\nFinal constraint equation: { } = { }\nImported 3 cells to SAT database.\nImport proof-constraint: \\bad = 1'0\nFinal proof equation: \\bad = 1'0\n\nSetting up time step 3:\nFinal constraint equation: { } = { }\nImported 3 cells to SAT database.\nImport proof-constraint: \\bad = 1'0\nFinal proof equation: \\bad = 1'0\n\nSetting up time step 4:\nFinal constraint equation: { } = { }\nImported 3 cells to SAT database.\nImport proof-constraint: \\bad = 1'0\nFinal proof equation: \\bad = 1'0\n\nSetting up time step 5:\nFinal constraint equation: { } = { }\nImported 3 cells to SAT database.\nImport proof-constraint: \\bad = 1'0\nFinal proof equation: \\bad = 1'0\n\nSetting up time step 6:\nFinal constraint equation: { } = { }\nImported 3 cells to SAT database.\nImport proof-constraint: \\bad = 1'0\nFinal proof equation: \\bad = 1'0\nImport show expression: \\clk\nImport show expression: \\bad\nImport show expression: \\count\n\nSolving problem with 274 variables and 733 clauses..\nSAT proof finished - model found: FAIL!\n\n ______ ___ ___ _ _ _ _ \n (_____ \\ / __) / __) (_) | | | |\n _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | |\n | ____/ ___) _ \\ / _ (_ __) (_ __|____ | | || ___ |/ _ |_|\n | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ \n |_| |_| \\___/ \\___/ |_| |_| \\_____|_|\\_)_____)\\____|_|\n\n\n Time Signal Name Dec Hex Bin\n ---- --------------- ----------- --------- -------------\n init \\cycles 0 0 000\n ---- --------------- ----------- --------- -------------\n 1 \\bad 0 0 0\n 1 \\clk 0 0 0\n 1 \\count 0 0 000\n ---- --------------- ----------- --------- -------------\n 2 \\bad 0 0 0\n 2 \\clk 0 0 0\n 2 \\count 1 1 001\n ---- --------------- ----------- --------- -------------\n 3 \\bad 0 0 0\n 3 \\clk 0 0 0\n 3 \\count 2 2 010\n ---- --------------- ----------- --------- -------------\n 4 \\bad 0 0 0\n 4 \\clk 0 0 0\n 4 \\count 3 3 011\n ---- --------------- ----------- --------- -------------\n 5 \\bad 0 0 0\n 5 \\clk 0 0 0\n 5 \\count 4 4 100\n ---- --------------- ----------- --------- -------------\n 6 \\bad 1 1 1\n 6 \\clk 0 0 0\n 6 \\count 5 5 101\nDumping SAT model to WaveJSON file 'deeper_6.json'.\n", "stderr": "", "input_sha256": { "masked_bounded.ys": "bdf178d6f6c134c23ec056dfe99ad2095ba2b620a1f6f3b3034bd279a5688164", "strengthened_induction.ys": "c0f9849e3ed933ca38ff6a961adbbb08017f360266a684d29f70f61a6d627d11", "induction.sv": "31bfa2953dcfa67a352feb3bee5def35e0944c46caaf00326ee1a8dca4e486e6", "weak_induction.ys": "0c9564190e299dda044a38efa0dd59261d8f72b68d79147caf1e1cf04af960e2", "bounded_5.ys": "827a75335345d035df12c9d3ab0d1b06fcf6c79361bd3de5a7e64ad84cf7869d", "cover_unmasked.ys": "bcfcf94773673c7dde5237346acbcf416a5fa1821a308554c66b5dc9317de9a4", "deeper_6.ys": "b3e328858b39a400de7ebdff4170fb85843cb5746f307c628b8df66d4727a764", "masked_bug.sv": "44c0ab027ad89a94a5856227adcf4d4d01dffce43e634c8840fe68b31b3818c7", "cover_masked.ys": "7a78e789233cb208939ecb7267ac42a099e427c6179700ac6278774556a34bf9", "weak_induction_depth2.ys": "8b71caad233b5b514ba990032c06b6f7afdd0a042a76d484b660026554f56cfd", "late_bug.sv": "b2e71f3b573a9e6fb45ea383dca35c786c8c95492c84af8ed89a119acd8b2365" } }, { "case": "masked_bounded", "started_at_utc": "2026-10-25T14:29:51.808135+00:00", "ended_at_utc": "2026-10-25T14:29:51.818406+00:00", "command": [ "${TOOL_WORKSPACE}/runtime/formal-tools/cellar/yosys/0.70/bin/yosys", "-Q", "-T", "-s", "masked_bounded.ys" ], "return_code": 0, "stdout": "\n-- Executing script file `masked_bounded.ys' --\n\n1. Executing Verilog-2005 frontend: masked_bug.sv\nParsing formal SystemVerilog input from `masked_bug.sv' to AST representation.\nGenerating RTLIL representation for module `\\masked_bug'.\nSuccessfully finished Verilog frontend.\n\n2. Executing PREP pass.\n\n2.1. Executing HIERARCHY pass (managing design hierarchy).\n\n2.1.1. Analyzing design hierarchy..\nTop module: \\masked_bug\n\n2.1.2. Analyzing design hierarchy..\nTop module: \\masked_bug\nRemoved 0 unused modules.\nModule masked_bug directly or indirectly contains formal properties -> setting \"keep\" attribute.\n\n2.2. Executing PROC pass (convert processes to netlists).\n\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nCleaned up 0 empty switches.\n\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nRemoved a total of 0 dead cases.\n\n2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 2 redundant assignments.\nPromoted 3 assignments to connections.\n\n2.2.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\masked_bug.$proc$masked_bug.sv:4$8'.\n Set init value: \\accepted = 3'000\n\n2.2.5. Executing PROC_ARST pass (detect async resets in processes).\n\n2.2.6. Executing PROC_ROM pass (convert switches to ROMs).\nConverted 0 switches.\n\n\n2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:4$8'.\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:8$4'.\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:5$1'.\n 1/1: $0\\accepted[2:0]\n\n2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).\n\n2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\masked_bug.\\accepted' using process `\\masked_bug.$proc$masked_bug.sv:5$1'.\n created $dff cell `$procdff$11' with positive edge clock.\n\n2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).\n\n2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `masked_bug.$proc$masked_bug.sv:4$8'.\nRemoving empty process `masked_bug.$proc$masked_bug.sv:8$4'.\nFound and cleaned up 1 empty switch in `\\masked_bug.$proc$masked_bug.sv:5$1'.\nRemoving empty process `masked_bug.$proc$masked_bug.sv:5$1'.\nCleaned up 1 empty switch.\n\n2.2.12. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.3. Executing FUTURE pass.\n\n2.4. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.5. Executing CHECK pass (checking for obvious problems).\nChecking module masked_bug...\nFound and reported 0 problems.\n\n2.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\nRemoved 0 unused cells and 6 unused wires.\n\n\n2.7. Executing OPT pass (performing simple optimizations).\n\n2.7.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.7.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\masked_bug..\n Creating internal representation of mux trees.\n Evaluating internal representation of mux trees.\n Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n\n\n2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\masked_bug.\nPerformed a total of 0 changes.\n\n2.7.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.7.7. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.7.8. Finished fast OPT passes. (There is nothing left to do.)\n\n2.8. Executing WREDUCE pass (reducing word size of cells).\nRemoved top 1 bits (of 3) from port B of cell masked_bug.$eq$masked_bug.sv:7$3 ($eq).\n\n2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.10. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n2.11. Executing OPT pass (performing simple optimizations).\n\n2.11.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.11.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.11.4. Finished fast OPT passes.\n\n2.12. Executing SORT pass.\n\n2.13. Printing statistics.\n\n=== masked_bug ===\n\n +----------Local Count, excluding submodules.\n | \n 8 wires\n 16 wire bits\n 5 public wires\n 9 public wire bits\n 4 ports\n 6 port bits\n 7 cells\n 1 $add\n 2 $check\n 1 $dff\n 1 $eq\n 1 $logic_not\n 1 $mux\n\n2.14. Executing CHECK pass (checking for obvious problems).\nChecking module masked_bug...\nFound and reported 0 problems.\n\n3. Executing SAT pass (solving SAT problems in the circuit).\nUsing SAT solver `minisat`.\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport constraint from assume cell: $logic_not$masked_bug.sv:9$6_Y when 1'1.\nImport set-constraint from init attribute: \\accepted = 3'000\nFinal init constraint equation: \\accepted = 3'000\nImport proof-constraint: \\target = 1'0\nFinal proof equation: \\target = 1'0\n\nSetting up time step 2:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport constraint from assume cell: $logic_not$masked_bug.sv:9$6_Y when 1'1.\nImport proof-constraint: \\target = 1'0\nFinal proof equation: \\target = 1'0\n\nSetting up time step 3:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport constraint from assume cell: $logic_not$masked_bug.sv:9$6_Y when 1'1.\nImport proof-constraint: \\target = 1'0\nFinal proof equation: \\target = 1'0\n\nSetting up time step 4:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport constraint from assume cell: $logic_not$masked_bug.sv:9$6_Y when 1'1.\nImport proof-constraint: \\target = 1'0\nFinal proof equation: \\target = 1'0\n\nSetting up time step 5:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport constraint from assume cell: $logic_not$masked_bug.sv:9$6_Y when 1'1.\nImport proof-constraint: \\target = 1'0\nFinal proof equation: \\target = 1'0\n\nSetting up time step 6:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport constraint from assume cell: $logic_not$masked_bug.sv:9$6_Y when 1'1.\nImport proof-constraint: \\target = 1'0\nFinal proof equation: \\target = 1'0\nImport show expression: \\clk\nImport show expression: \\fire\nImport show expression: \\count\nImport show expression: \\target\n\nSolving problem with 507 variables and 1336 clauses..\nSAT proof finished - no model found: SUCCESS!\n\n /$$$$$$ /$$$$$$$$ /$$$$$$$ \n /$$__ $$ | $$_____/ | $$__ $$ \n | $$ \\ $$ | $$ | $$ \\ $$ \n | $$ | $$ | $$$$$ | $$ | $$ \n | $$ | $$ | $$__/ | $$ | $$ \n | $$/$$ $$ | $$ | $$ | $$ \n | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$\n \\____ $$$|__/|________/|__/|_______/|__/\n \\__/ \n\n", "stderr": "", "input_sha256": { "masked_bounded.ys": "bdf178d6f6c134c23ec056dfe99ad2095ba2b620a1f6f3b3034bd279a5688164", "strengthened_induction.ys": "c0f9849e3ed933ca38ff6a961adbbb08017f360266a684d29f70f61a6d627d11", "induction.sv": "31bfa2953dcfa67a352feb3bee5def35e0944c46caaf00326ee1a8dca4e486e6", "weak_induction.ys": "0c9564190e299dda044a38efa0dd59261d8f72b68d79147caf1e1cf04af960e2", "bounded_5.ys": "827a75335345d035df12c9d3ab0d1b06fcf6c79361bd3de5a7e64ad84cf7869d", "cover_unmasked.ys": "bcfcf94773673c7dde5237346acbcf416a5fa1821a308554c66b5dc9317de9a4", "deeper_6.ys": "b3e328858b39a400de7ebdff4170fb85843cb5746f307c628b8df66d4727a764", "masked_bug.sv": "44c0ab027ad89a94a5856227adcf4d4d01dffce43e634c8840fe68b31b3818c7", "cover_masked.ys": "7a78e789233cb208939ecb7267ac42a099e427c6179700ac6278774556a34bf9", "weak_induction_depth2.ys": "8b71caad233b5b514ba990032c06b6f7afdd0a042a76d484b660026554f56cfd", "late_bug.sv": "b2e71f3b573a9e6fb45ea383dca35c786c8c95492c84af8ed89a119acd8b2365" } }, { "case": "cover_masked", "started_at_utc": "2026-10-25T14:29:51.823446+00:00", "ended_at_utc": "2026-10-25T14:29:51.832921+00:00", "command": [ "${TOOL_WORKSPACE}/runtime/formal-tools/cellar/yosys/0.70/bin/yosys", "-Q", "-T", "-s", "cover_masked.ys" ], "return_code": 0, "stdout": "\n-- Executing script file `cover_masked.ys' --\n\n1. Executing Verilog-2005 frontend: masked_bug.sv\nParsing formal SystemVerilog input from `masked_bug.sv' to AST representation.\nGenerating RTLIL representation for module `\\masked_bug'.\nSuccessfully finished Verilog frontend.\n\n2. Executing PREP pass.\n\n2.1. Executing HIERARCHY pass (managing design hierarchy).\n\n2.1.1. Analyzing design hierarchy..\nTop module: \\masked_bug\n\n2.1.2. Analyzing design hierarchy..\nTop module: \\masked_bug\nRemoved 0 unused modules.\nModule masked_bug directly or indirectly contains formal properties -> setting \"keep\" attribute.\n\n2.2. Executing PROC pass (convert processes to netlists).\n\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nCleaned up 0 empty switches.\n\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nRemoved a total of 0 dead cases.\n\n2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 2 redundant assignments.\nPromoted 3 assignments to connections.\n\n2.2.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\masked_bug.$proc$masked_bug.sv:4$8'.\n Set init value: \\accepted = 3'000\n\n2.2.5. Executing PROC_ARST pass (detect async resets in processes).\n\n2.2.6. Executing PROC_ROM pass (convert switches to ROMs).\nConverted 0 switches.\n\n\n2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:4$8'.\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:8$4'.\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:5$1'.\n 1/1: $0\\accepted[2:0]\n\n2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).\n\n2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\masked_bug.\\accepted' using process `\\masked_bug.$proc$masked_bug.sv:5$1'.\n created $dff cell `$procdff$11' with positive edge clock.\n\n2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).\n\n2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `masked_bug.$proc$masked_bug.sv:4$8'.\nRemoving empty process `masked_bug.$proc$masked_bug.sv:8$4'.\nFound and cleaned up 1 empty switch in `\\masked_bug.$proc$masked_bug.sv:5$1'.\nRemoving empty process `masked_bug.$proc$masked_bug.sv:5$1'.\nCleaned up 1 empty switch.\n\n2.2.12. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.3. Executing FUTURE pass.\n\n2.4. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.5. Executing CHECK pass (checking for obvious problems).\nChecking module masked_bug...\nFound and reported 0 problems.\n\n2.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\nRemoved 0 unused cells and 6 unused wires.\n\n\n2.7. Executing OPT pass (performing simple optimizations).\n\n2.7.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.7.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\masked_bug..\n Creating internal representation of mux trees.\n Evaluating internal representation of mux trees.\n Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n\n\n2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\masked_bug.\nPerformed a total of 0 changes.\n\n2.7.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.7.7. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.7.8. Finished fast OPT passes. (There is nothing left to do.)\n\n2.8. Executing WREDUCE pass (reducing word size of cells).\nRemoved top 1 bits (of 3) from port B of cell masked_bug.$eq$masked_bug.sv:7$3 ($eq).\n\n2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.10. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n2.11. Executing OPT pass (performing simple optimizations).\n\n2.11.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.11.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.11.4. Finished fast OPT passes.\n\n2.12. Executing SORT pass.\n\n2.13. Printing statistics.\n\n=== masked_bug ===\n\n +----------Local Count, excluding submodules.\n | \n 8 wires\n 16 wire bits\n 5 public wires\n 9 public wire bits\n 4 ports\n 6 port bits\n 7 cells\n 1 $add\n 2 $check\n 1 $dff\n 1 $eq\n 1 $logic_not\n 1 $mux\n\n2.14. Executing CHECK pass (checking for obvious problems).\nChecking module masked_bug...\nFound and reported 0 problems.\n\n3. Executing SAT pass (solving SAT problems in the circuit).\nUsing SAT solver `minisat`.\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport constraint from assume cell: $logic_not$masked_bug.sv:9$6_Y when 1'1.\nImport set-constraint from init attribute: \\accepted = 3'000\nFinal init constraint equation: \\accepted = 3'000\n\nSetting up time step 2:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport constraint from assume cell: $logic_not$masked_bug.sv:9$6_Y when 1'1.\n\nSetting up time step 3:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport constraint from assume cell: $logic_not$masked_bug.sv:9$6_Y when 1'1.\n\nSetting up time step 4:\nImport set-constraint for this timestep: \\target = 1'1\nFinal constraint equation: \\target = 1'1\nImported 9 cells to SAT database.\nImport constraint from assume cell: $logic_not$masked_bug.sv:9$6_Y when 1'1.\nImport show expression: \\clk\nImport show expression: \\fire\nImport show expression: \\count\nImport show expression: \\target\n\nSolving problem with 330 variables and 862 clauses..\nSAT solving finished - no model found.\n", "stderr": "", "input_sha256": { "masked_bounded.ys": "bdf178d6f6c134c23ec056dfe99ad2095ba2b620a1f6f3b3034bd279a5688164", "strengthened_induction.ys": "c0f9849e3ed933ca38ff6a961adbbb08017f360266a684d29f70f61a6d627d11", "induction.sv": "31bfa2953dcfa67a352feb3bee5def35e0944c46caaf00326ee1a8dca4e486e6", "weak_induction.ys": "0c9564190e299dda044a38efa0dd59261d8f72b68d79147caf1e1cf04af960e2", "bounded_5.ys": "827a75335345d035df12c9d3ab0d1b06fcf6c79361bd3de5a7e64ad84cf7869d", "cover_unmasked.ys": "bcfcf94773673c7dde5237346acbcf416a5fa1821a308554c66b5dc9317de9a4", "deeper_6.ys": "b3e328858b39a400de7ebdff4170fb85843cb5746f307c628b8df66d4727a764", "masked_bug.sv": "44c0ab027ad89a94a5856227adcf4d4d01dffce43e634c8840fe68b31b3818c7", "cover_masked.ys": "7a78e789233cb208939ecb7267ac42a099e427c6179700ac6278774556a34bf9", "weak_induction_depth2.ys": "8b71caad233b5b514ba990032c06b6f7afdd0a042a76d484b660026554f56cfd", "late_bug.sv": "b2e71f3b573a9e6fb45ea383dca35c786c8c95492c84af8ed89a119acd8b2365" } }, { "case": "cover_unmasked", "started_at_utc": "2026-10-25T14:29:51.836034+00:00", "ended_at_utc": "2026-10-25T14:29:51.845661+00:00", "command": [ "${TOOL_WORKSPACE}/runtime/formal-tools/cellar/yosys/0.70/bin/yosys", "-Q", "-T", "-s", "cover_unmasked.ys" ], "return_code": 0, "stdout": "\n-- Executing script file `cover_unmasked.ys' --\n\n1. Executing Verilog-2005 frontend: masked_bug.sv\nParsing formal SystemVerilog input from `masked_bug.sv' to AST representation.\nGenerating RTLIL representation for module `\\masked_bug'.\nSuccessfully finished Verilog frontend.\n\n2. Executing PREP pass.\n\n2.1. Executing HIERARCHY pass (managing design hierarchy).\n\n2.1.1. Analyzing design hierarchy..\nTop module: \\masked_bug\n\n2.1.2. Analyzing design hierarchy..\nTop module: \\masked_bug\nRemoved 0 unused modules.\nModule masked_bug directly or indirectly contains formal properties -> setting \"keep\" attribute.\n\n2.2. Executing PROC pass (convert processes to netlists).\n\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nCleaned up 0 empty switches.\n\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nRemoved a total of 0 dead cases.\n\n2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 2 redundant assignments.\nPromoted 3 assignments to connections.\n\n2.2.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\masked_bug.$proc$masked_bug.sv:4$8'.\n Set init value: \\accepted = 3'000\n\n2.2.5. Executing PROC_ARST pass (detect async resets in processes).\n\n2.2.6. Executing PROC_ROM pass (convert switches to ROMs).\nConverted 0 switches.\n\n\n2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:4$8'.\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:8$4'.\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:5$1'.\n 1/1: $0\\accepted[2:0]\n\n2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).\n\n2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\masked_bug.\\accepted' using process `\\masked_bug.$proc$masked_bug.sv:5$1'.\n created $dff cell `$procdff$11' with positive edge clock.\n\n2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).\n\n2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `masked_bug.$proc$masked_bug.sv:4$8'.\nRemoving empty process `masked_bug.$proc$masked_bug.sv:8$4'.\nFound and cleaned up 1 empty switch in `\\masked_bug.$proc$masked_bug.sv:5$1'.\nRemoving empty process `masked_bug.$proc$masked_bug.sv:5$1'.\nCleaned up 1 empty switch.\n\n2.2.12. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.3. Executing FUTURE pass.\n\n2.4. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.5. Executing CHECK pass (checking for obvious problems).\nChecking module masked_bug...\nFound and reported 0 problems.\n\n2.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\nRemoved 0 unused cells and 6 unused wires.\n\n\n2.7. Executing OPT pass (performing simple optimizations).\n\n2.7.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.7.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\masked_bug..\n Creating internal representation of mux trees.\n Evaluating internal representation of mux trees.\n Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n\n\n2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\masked_bug.\nPerformed a total of 0 changes.\n\n2.7.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.7.7. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.7.8. Finished fast OPT passes. (There is nothing left to do.)\n\n2.8. Executing WREDUCE pass (reducing word size of cells).\nRemoved top 1 bits (of 3) from port B of cell masked_bug.$eq$masked_bug.sv:7$3 ($eq).\n\n2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.10. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n2.11. Executing OPT pass (performing simple optimizations).\n\n2.11.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.11.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.11.4. Finished fast OPT passes.\n\n2.12. Executing SORT pass.\n\n2.13. Printing statistics.\n\n=== masked_bug ===\n\n +----------Local Count, excluding submodules.\n | \n 8 wires\n 16 wire bits\n 5 public wires\n 9 public wire bits\n 4 ports\n 6 port bits\n 7 cells\n 1 $add\n 2 $check\n 1 $dff\n 1 $eq\n 1 $logic_not\n 1 $mux\n\n2.14. Executing CHECK pass (checking for obvious problems).\nChecking module masked_bug...\nFound and reported 0 problems.\n\n3. Executing SAT pass (solving SAT problems in the circuit).\nUsing SAT solver `minisat`.\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport set-constraint from init attribute: \\accepted = 3'000\nFinal init constraint equation: \\accepted = 3'000\n\nSetting up time step 2:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\n\nSetting up time step 3:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\n\nSetting up time step 4:\nImport set-constraint for this timestep: \\target = 1'1\nFinal constraint equation: \\target = 1'1\nImported 9 cells to SAT database.\nImport show expression: \\clk\nImport show expression: \\fire\nImport show expression: \\count\nImport show expression: \\target\n\nSolving problem with 330 variables and 858 clauses..\nSAT solving finished - model found:\n\n Time Signal Name Dec Hex Bin\n ---- --------------- ----------- --------- -------------\n init \\accepted 0 0 000\n ---- --------------- ----------- --------- -------------\n 1 \\clk 0 0 0\n 1 \\count 0 0 000\n 1 \\fire 1 1 1\n 1 \\target 0 0 0\n ---- --------------- ----------- --------- -------------\n 2 \\clk 0 0 0\n 2 \\count 1 1 001\n 2 \\fire 1 1 1\n 2 \\target 0 0 0\n ---- --------------- ----------- --------- -------------\n 3 \\clk 0 0 0\n 3 \\count 2 2 010\n 3 \\fire 1 1 1\n 3 \\target 0 0 0\n ---- --------------- ----------- --------- -------------\n 4 \\clk 0 0 0\n 4 \\count 3 3 011\n 4 \\fire 0 0 0\n 4 \\target 1 1 1\nDumping SAT model to WaveJSON file 'cover_unmasked.json'.\n", "stderr": "", "input_sha256": { "masked_bounded.ys": "bdf178d6f6c134c23ec056dfe99ad2095ba2b620a1f6f3b3034bd279a5688164", "strengthened_induction.ys": "c0f9849e3ed933ca38ff6a961adbbb08017f360266a684d29f70f61a6d627d11", "induction.sv": "31bfa2953dcfa67a352feb3bee5def35e0944c46caaf00326ee1a8dca4e486e6", "weak_induction.ys": "0c9564190e299dda044a38efa0dd59261d8f72b68d79147caf1e1cf04af960e2", "bounded_5.ys": "827a75335345d035df12c9d3ab0d1b06fcf6c79361bd3de5a7e64ad84cf7869d", "cover_unmasked.ys": "bcfcf94773673c7dde5237346acbcf416a5fa1821a308554c66b5dc9317de9a4", "deeper_6.ys": "b3e328858b39a400de7ebdff4170fb85843cb5746f307c628b8df66d4727a764", "masked_bug.sv": "44c0ab027ad89a94a5856227adcf4d4d01dffce43e634c8840fe68b31b3818c7", "cover_masked.ys": "7a78e789233cb208939ecb7267ac42a099e427c6179700ac6278774556a34bf9", "weak_induction_depth2.ys": "8b71caad233b5b514ba990032c06b6f7afdd0a042a76d484b660026554f56cfd", "late_bug.sv": "b2e71f3b573a9e6fb45ea383dca35c786c8c95492c84af8ed89a119acd8b2365" } }, { "case": "weak_induction", "started_at_utc": "2026-10-25T14:29:51.848239+00:00", "ended_at_utc": "2026-10-25T14:29:51.857942+00:00", "command": [ "${TOOL_WORKSPACE}/runtime/formal-tools/cellar/yosys/0.70/bin/yosys", "-Q", "-T", "-s", "weak_induction.ys" ], "return_code": 0, "stdout": "\n-- Executing script file `weak_induction.ys' --\n\n1. Executing Verilog-2005 frontend: induction.sv\nParsing formal SystemVerilog input from `induction.sv' to AST representation.\nGenerating RTLIL representation for module `\\induction'.\nSuccessfully finished Verilog frontend.\n\n2. Executing PREP pass.\n\n2.1. Executing HIERARCHY pass (managing design hierarchy).\n\n2.1.1. Analyzing design hierarchy..\nTop module: \\induction\n\n2.1.2. Analyzing design hierarchy..\nTop module: \\induction\nRemoved 0 unused modules.\n\n2.2. Executing PROC pass (convert processes to netlists).\n\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nCleaned up 0 empty switches.\n\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nRemoved a total of 0 dead cases.\n\n2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 0 redundant assignments.\nPromoted 3 assignments to connections.\n\n2.2.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\induction.$proc$induction.sv:5$10'.\n Set init value: \\b = 4'0000\nFound init rule in `\\induction.$proc$induction.sv:4$9'.\n Set init value: \\a = 4'0000\n\n2.2.5. Executing PROC_ARST pass (detect async resets in processes).\n\n2.2.6. Executing PROC_ROM pass (convert switches to ROMs).\nConverted 0 switches.\n\n\n2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\induction.$proc$induction.sv:5$10'.\nCreating decoders for process `\\induction.$proc$induction.sv:4$9'.\nCreating decoders for process `\\induction.$proc$induction.sv:6$1'.\n 1/1: $0\\b[3:0]\n\n2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).\n\n2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\induction.\\a' using process `\\induction.$proc$induction.sv:6$1'.\n created $dff cell `$procdff$13' with positive edge clock.\nCreating register for signal `\\induction.\\b' using process `\\induction.$proc$induction.sv:6$1'.\n created $dff cell `$procdff$14' with positive edge clock.\n\n2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).\n\n2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `induction.$proc$induction.sv:5$10'.\nRemoving empty process `induction.$proc$induction.sv:4$9'.\nFound and cleaned up 1 empty switch in `\\induction.$proc$induction.sv:6$1'.\nRemoving empty process `induction.$proc$induction.sv:6$1'.\nCleaned up 1 empty switch.\n\n2.2.12. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n\n2.3. Executing FUTURE pass.\n\n2.4. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.5. Executing CHECK pass (checking for obvious problems).\nChecking module induction...\nFound and reported 0 problems.\n\n2.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\nRemoved 0 unused cells and 7 unused wires.\n\n\n2.7. Executing OPT pass (performing simple optimizations).\n\n2.7.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.7.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\induction'.\nComputing hashes of 10 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\nComputing hashes of 9 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\n\nRemoved a total of 1 cells.\n\n2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\induction..\n Creating internal representation of mux trees.\n Evaluating internal representation of mux trees.\n Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n\n\n2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\induction.\nPerformed a total of 0 changes.\n\n2.7.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\induction'.\nComputing hashes of 9 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\nRemoved a total of 0 cells.\n\n2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\nRemoved 0 unused cells and 1 unused wires.\n\n\n2.7.7. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.7.8. Rerunning OPT passes. (Maybe there is more to do..)\n\n2.7.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\induction..\n Creating internal representation of mux trees.\n Evaluating internal representation of mux trees.\n Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n\n\n2.7.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\induction.\nPerformed a total of 0 changes.\n\n2.7.11. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\induction'.\nComputing hashes of 9 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\nRemoved a total of 0 cells.\n\n2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\n\n2.7.13. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.7.14. Finished fast OPT passes. (There is nothing left to do.)\n\n2.8. Executing WREDUCE pass (reducing word size of cells).\n\n2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\n\n2.10. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n2.11. Executing OPT pass (performing simple optimizations).\n\n2.11.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.11.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\induction'.\nComputing hashes of 9 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\nRemoved a total of 0 cells.\n\n2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\n\n2.11.4. Finished fast OPT passes.\n\n2.12. Executing SORT pass.\n\n2.13. Printing statistics.\n\n=== induction ===\n\n +----------Local Count, excluding submodules.\n | \n 13 wires\n 31 wire bits\n 8 public wires\n 20 public wire bits\n 6 ports\n 12 port bits\n 9 cells\n 1 $add\n 2 $dff\n 2 $logic_and\n 2 $logic_not\n 1 $mux\n 1 $reduce_bool\n\n2.14. Executing CHECK pass (checking for obvious problems).\nChecking module induction...\nFound and reported 0 problems.\n\n3. Executing SAT pass (solving SAT problems in the circuit).\nUsing SAT solver `minisat`.\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport proof-constraint: \\weak_ok = 1'1\nFinal proof equation: \\weak_ok = 1'1\n\n** Trying induction with length 1 **\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport set-constraint from init attribute: \\a = 4'0000\nImport set-constraint from init attribute: \\b = 4'0000\nFinal init constraint equation: { \\b \\a } = 8'00000000\nImport proof-constraint: \\weak_ok = 1'1\nFinal proof equation: \\weak_ok = 1'1\nImport show expression: \\advance\nImport show expression: \\clk\nImport show expression: \\hidden\nImport show expression: \\strong_ok\nImport show expression: \\visible\nImport show expression: \\weak_ok\n\n[base case 1] Solving problem with 111 variables and 286 clauses..\nBase case for induction length 1 proven.\n\nSetting up time step 2:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport proof-constraint: \\weak_ok = 1'1\nFinal proof equation: \\weak_ok = 1'1\nImport show expression: \\advance\nImport show expression: \\clk\nImport show expression: \\hidden\nImport show expression: \\strong_ok\nImport show expression: \\visible\nImport show expression: \\weak_ok\n\n[induction step 1] Solving problem with 218 variables and 557 clauses..\nInduction step failed. Incrementing induction length.\n\n Time Signal Name Dec Hex Bin\n ---- --------------- ----------- --------- -------------\n init \\a 0 0 0000\n init \\b 14 e 1110\n ---- --------------- ----------- --------- -------------\n 1 \\advance 1 1 1\n 1 \\clk 0 0 0\n 1 \\hidden 14 e 1110\n 1 \\strong_ok 0 0 0\n 1 \\visible 0 0 0000\n 1 \\weak_ok 1 1 1\n ---- --------------- ----------- --------- -------------\n 2 \\advance 1 1 1\n 2 \\clk 0 0 0\n 2 \\hidden 15 f 1111\n 2 \\strong_ok 0 0 0\n 2 \\visible 14 e 1110\n 2 \\weak_ok 0 0 0\n\nReached maximum number of time steps -> proof failed.\nDumping SAT model to WaveJSON file 'weak_induction.json'.\n\n ______ ___ ___ _ _ _ _ \n (_____ \\ / __) / __) (_) | | | |\n _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | |\n | ____/ ___) _ \\ / _ (_ __) (_ __|____ | | || ___ |/ _ |_|\n | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ \n |_| |_| \\___/ \\___/ |_| |_| \\_____|_|\\_)_____)\\____|_|\n\n", "stderr": "", "input_sha256": { "masked_bounded.ys": "bdf178d6f6c134c23ec056dfe99ad2095ba2b620a1f6f3b3034bd279a5688164", "strengthened_induction.ys": "c0f9849e3ed933ca38ff6a961adbbb08017f360266a684d29f70f61a6d627d11", "induction.sv": "31bfa2953dcfa67a352feb3bee5def35e0944c46caaf00326ee1a8dca4e486e6", "weak_induction.ys": "0c9564190e299dda044a38efa0dd59261d8f72b68d79147caf1e1cf04af960e2", "bounded_5.ys": "827a75335345d035df12c9d3ab0d1b06fcf6c79361bd3de5a7e64ad84cf7869d", "cover_unmasked.ys": "bcfcf94773673c7dde5237346acbcf416a5fa1821a308554c66b5dc9317de9a4", "deeper_6.ys": "b3e328858b39a400de7ebdff4170fb85843cb5746f307c628b8df66d4727a764", "masked_bug.sv": "44c0ab027ad89a94a5856227adcf4d4d01dffce43e634c8840fe68b31b3818c7", "cover_masked.ys": "7a78e789233cb208939ecb7267ac42a099e427c6179700ac6278774556a34bf9", "weak_induction_depth2.ys": "8b71caad233b5b514ba990032c06b6f7afdd0a042a76d484b660026554f56cfd", "late_bug.sv": "b2e71f3b573a9e6fb45ea383dca35c786c8c95492c84af8ed89a119acd8b2365" } }, { "case": "strengthened_induction", "started_at_utc": "2026-10-25T14:29:51.860584+00:00", "ended_at_utc": "2026-10-25T14:29:51.870316+00:00", "command": [ "${TOOL_WORKSPACE}/runtime/formal-tools/cellar/yosys/0.70/bin/yosys", "-Q", "-T", "-s", "strengthened_induction.ys" ], "return_code": 0, "stdout": "\n-- Executing script file `strengthened_induction.ys' --\n\n1. Executing Verilog-2005 frontend: induction.sv\nParsing formal SystemVerilog input from `induction.sv' to AST representation.\nGenerating RTLIL representation for module `\\induction'.\nSuccessfully finished Verilog frontend.\n\n2. Executing PREP pass.\n\n2.1. Executing HIERARCHY pass (managing design hierarchy).\n\n2.1.1. Analyzing design hierarchy..\nTop module: \\induction\n\n2.1.2. Analyzing design hierarchy..\nTop module: \\induction\nRemoved 0 unused modules.\n\n2.2. Executing PROC pass (convert processes to netlists).\n\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nCleaned up 0 empty switches.\n\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nRemoved a total of 0 dead cases.\n\n2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 0 redundant assignments.\nPromoted 3 assignments to connections.\n\n2.2.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\induction.$proc$induction.sv:5$10'.\n Set init value: \\b = 4'0000\nFound init rule in `\\induction.$proc$induction.sv:4$9'.\n Set init value: \\a = 4'0000\n\n2.2.5. Executing PROC_ARST pass (detect async resets in processes).\n\n2.2.6. Executing PROC_ROM pass (convert switches to ROMs).\nConverted 0 switches.\n\n\n2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\induction.$proc$induction.sv:5$10'.\nCreating decoders for process `\\induction.$proc$induction.sv:4$9'.\nCreating decoders for process `\\induction.$proc$induction.sv:6$1'.\n 1/1: $0\\b[3:0]\n\n2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).\n\n2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\induction.\\a' using process `\\induction.$proc$induction.sv:6$1'.\n created $dff cell `$procdff$13' with positive edge clock.\nCreating register for signal `\\induction.\\b' using process `\\induction.$proc$induction.sv:6$1'.\n created $dff cell `$procdff$14' with positive edge clock.\n\n2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).\n\n2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `induction.$proc$induction.sv:5$10'.\nRemoving empty process `induction.$proc$induction.sv:4$9'.\nFound and cleaned up 1 empty switch in `\\induction.$proc$induction.sv:6$1'.\nRemoving empty process `induction.$proc$induction.sv:6$1'.\nCleaned up 1 empty switch.\n\n2.2.12. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n\n2.3. Executing FUTURE pass.\n\n2.4. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.5. Executing CHECK pass (checking for obvious problems).\nChecking module induction...\nFound and reported 0 problems.\n\n2.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\nRemoved 0 unused cells and 7 unused wires.\n\n\n2.7. Executing OPT pass (performing simple optimizations).\n\n2.7.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.7.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\induction'.\nComputing hashes of 10 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\nComputing hashes of 9 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\n\nRemoved a total of 1 cells.\n\n2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\induction..\n Creating internal representation of mux trees.\n Evaluating internal representation of mux trees.\n Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n\n\n2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\induction.\nPerformed a total of 0 changes.\n\n2.7.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\induction'.\nComputing hashes of 9 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\nRemoved a total of 0 cells.\n\n2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\nRemoved 0 unused cells and 1 unused wires.\n\n\n2.7.7. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.7.8. Rerunning OPT passes. (Maybe there is more to do..)\n\n2.7.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\induction..\n Creating internal representation of mux trees.\n Evaluating internal representation of mux trees.\n Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n\n\n2.7.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\induction.\nPerformed a total of 0 changes.\n\n2.7.11. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\induction'.\nComputing hashes of 9 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\nRemoved a total of 0 cells.\n\n2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\n\n2.7.13. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.7.14. Finished fast OPT passes. (There is nothing left to do.)\n\n2.8. Executing WREDUCE pass (reducing word size of cells).\n\n2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\n\n2.10. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n2.11. Executing OPT pass (performing simple optimizations).\n\n2.11.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.11.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\induction'.\nComputing hashes of 9 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\nRemoved a total of 0 cells.\n\n2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\n\n2.11.4. Finished fast OPT passes.\n\n2.12. Executing SORT pass.\n\n2.13. Printing statistics.\n\n=== induction ===\n\n +----------Local Count, excluding submodules.\n | \n 13 wires\n 31 wire bits\n 8 public wires\n 20 public wire bits\n 6 ports\n 12 port bits\n 9 cells\n 1 $add\n 2 $dff\n 2 $logic_and\n 2 $logic_not\n 1 $mux\n 1 $reduce_bool\n\n2.14. Executing CHECK pass (checking for obvious problems).\nChecking module induction...\nFound and reported 0 problems.\n\n3. Executing SAT pass (solving SAT problems in the circuit).\nUsing SAT solver `minisat`.\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport proof-constraint: \\strong_ok = 1'1\nFinal proof equation: \\strong_ok = 1'1\n\n** Trying induction with length 1 **\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport set-constraint from init attribute: \\a = 4'0000\nImport set-constraint from init attribute: \\b = 4'0000\nFinal init constraint equation: { \\b \\a } = 8'00000000\nImport proof-constraint: \\strong_ok = 1'1\nFinal proof equation: \\strong_ok = 1'1\nImport show expression: \\advance\nImport show expression: \\clk\nImport show expression: \\hidden\nImport show expression: \\strong_ok\nImport show expression: \\visible\nImport show expression: \\weak_ok\n\n[base case 1] Solving problem with 111 variables and 286 clauses..\nBase case for induction length 1 proven.\n\nSetting up time step 2:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport proof-constraint: \\strong_ok = 1'1\nFinal proof equation: \\strong_ok = 1'1\nImport show expression: \\advance\nImport show expression: \\clk\nImport show expression: \\hidden\nImport show expression: \\strong_ok\nImport show expression: \\visible\nImport show expression: \\weak_ok\n\n[induction step 1] Solving problem with 218 variables and 557 clauses..\nInduction step proven: SUCCESS!\n\n /$$$$$$ /$$$$$$$$ /$$$$$$$ \n /$$__ $$ | $$_____/ | $$__ $$ \n | $$ \\ $$ | $$ | $$ \\ $$ \n | $$ | $$ | $$$$$ | $$ | $$ \n | $$ | $$ | $$__/ | $$ | $$ \n | $$/$$ $$ | $$ | $$ | $$ \n | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$\n \\____ $$$|__/|________/|__/|_______/|__/\n \\__/ \n\n", "stderr": "", "input_sha256": { "masked_bounded.ys": "bdf178d6f6c134c23ec056dfe99ad2095ba2b620a1f6f3b3034bd279a5688164", "strengthened_induction.ys": "c0f9849e3ed933ca38ff6a961adbbb08017f360266a684d29f70f61a6d627d11", "induction.sv": "31bfa2953dcfa67a352feb3bee5def35e0944c46caaf00326ee1a8dca4e486e6", "weak_induction.ys": "0c9564190e299dda044a38efa0dd59261d8f72b68d79147caf1e1cf04af960e2", "bounded_5.ys": "827a75335345d035df12c9d3ab0d1b06fcf6c79361bd3de5a7e64ad84cf7869d", "cover_unmasked.ys": "bcfcf94773673c7dde5237346acbcf416a5fa1821a308554c66b5dc9317de9a4", "deeper_6.ys": "b3e328858b39a400de7ebdff4170fb85843cb5746f307c628b8df66d4727a764", "masked_bug.sv": "44c0ab027ad89a94a5856227adcf4d4d01dffce43e634c8840fe68b31b3818c7", "cover_masked.ys": "7a78e789233cb208939ecb7267ac42a099e427c6179700ac6278774556a34bf9", "weak_induction_depth2.ys": "8b71caad233b5b514ba990032c06b6f7afdd0a042a76d484b660026554f56cfd", "late_bug.sv": "b2e71f3b573a9e6fb45ea383dca35c786c8c95492c84af8ed89a119acd8b2365" } }, { "case": "weak_induction_depth2", "started_at_utc": "2026-10-25T14:29:51.872820+00:00", "ended_at_utc": "2026-10-25T14:29:51.882886+00:00", "command": [ "${TOOL_WORKSPACE}/runtime/formal-tools/cellar/yosys/0.70/bin/yosys", "-Q", "-T", "-s", "weak_induction_depth2.ys" ], "return_code": 0, "stdout": "\n-- Executing script file `weak_induction_depth2.ys' --\n\n1. Executing Verilog-2005 frontend: induction.sv\nParsing formal SystemVerilog input from `induction.sv' to AST representation.\nGenerating RTLIL representation for module `\\induction'.\nSuccessfully finished Verilog frontend.\n\n2. Executing PREP pass.\n\n2.1. Executing HIERARCHY pass (managing design hierarchy).\n\n2.1.1. Analyzing design hierarchy..\nTop module: \\induction\n\n2.1.2. Analyzing design hierarchy..\nTop module: \\induction\nRemoved 0 unused modules.\n\n2.2. Executing PROC pass (convert processes to netlists).\n\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nCleaned up 0 empty switches.\n\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nRemoved a total of 0 dead cases.\n\n2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 0 redundant assignments.\nPromoted 3 assignments to connections.\n\n2.2.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\induction.$proc$induction.sv:5$10'.\n Set init value: \\b = 4'0000\nFound init rule in `\\induction.$proc$induction.sv:4$9'.\n Set init value: \\a = 4'0000\n\n2.2.5. Executing PROC_ARST pass (detect async resets in processes).\n\n2.2.6. Executing PROC_ROM pass (convert switches to ROMs).\nConverted 0 switches.\n\n\n2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\induction.$proc$induction.sv:5$10'.\nCreating decoders for process `\\induction.$proc$induction.sv:4$9'.\nCreating decoders for process `\\induction.$proc$induction.sv:6$1'.\n 1/1: $0\\b[3:0]\n\n2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).\n\n2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\induction.\\a' using process `\\induction.$proc$induction.sv:6$1'.\n created $dff cell `$procdff$13' with positive edge clock.\nCreating register for signal `\\induction.\\b' using process `\\induction.$proc$induction.sv:6$1'.\n created $dff cell `$procdff$14' with positive edge clock.\n\n2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).\n\n2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `induction.$proc$induction.sv:5$10'.\nRemoving empty process `induction.$proc$induction.sv:4$9'.\nFound and cleaned up 1 empty switch in `\\induction.$proc$induction.sv:6$1'.\nRemoving empty process `induction.$proc$induction.sv:6$1'.\nCleaned up 1 empty switch.\n\n2.2.12. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n\n2.3. Executing FUTURE pass.\n\n2.4. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.5. Executing CHECK pass (checking for obvious problems).\nChecking module induction...\nFound and reported 0 problems.\n\n2.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\nRemoved 0 unused cells and 7 unused wires.\n\n\n2.7. Executing OPT pass (performing simple optimizations).\n\n2.7.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.7.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\induction'.\nComputing hashes of 10 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\nComputing hashes of 9 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\n\nRemoved a total of 1 cells.\n\n2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\induction..\n Creating internal representation of mux trees.\n Evaluating internal representation of mux trees.\n Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n\n\n2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\induction.\nPerformed a total of 0 changes.\n\n2.7.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\induction'.\nComputing hashes of 9 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\nRemoved a total of 0 cells.\n\n2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\nRemoved 0 unused cells and 1 unused wires.\n\n\n2.7.7. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.7.8. Rerunning OPT passes. (Maybe there is more to do..)\n\n2.7.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\induction..\n Creating internal representation of mux trees.\n Evaluating internal representation of mux trees.\n Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n\n\n2.7.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\induction.\nPerformed a total of 0 changes.\n\n2.7.11. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\induction'.\nComputing hashes of 9 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\nRemoved a total of 0 cells.\n\n2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\n\n2.7.13. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.7.14. Finished fast OPT passes. (There is nothing left to do.)\n\n2.8. Executing WREDUCE pass (reducing word size of cells).\n\n2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\n\n2.10. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n2.11. Executing OPT pass (performing simple optimizations).\n\n2.11.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module induction.\n\n2.11.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\induction'.\nComputing hashes of 9 cells of `\\induction'.\nFinding duplicate cells in `\\induction'.\nRemoved a total of 0 cells.\n\n2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\induction..\n\n2.11.4. Finished fast OPT passes.\n\n2.12. Executing SORT pass.\n\n2.13. Printing statistics.\n\n=== induction ===\n\n +----------Local Count, excluding submodules.\n | \n 13 wires\n 31 wire bits\n 8 public wires\n 20 public wire bits\n 6 ports\n 12 port bits\n 9 cells\n 1 $add\n 2 $dff\n 2 $logic_and\n 2 $logic_not\n 1 $mux\n 1 $reduce_bool\n\n2.14. Executing CHECK pass (checking for obvious problems).\nChecking module induction...\nFound and reported 0 problems.\n\n3. Executing SAT pass (solving SAT problems in the circuit).\nUsing SAT solver `minisat`.\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport proof-constraint: \\weak_ok = 1'1\nFinal proof equation: \\weak_ok = 1'1\n\n** Trying induction with length 1 **\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport set-constraint from init attribute: \\a = 4'0000\nImport set-constraint from init attribute: \\b = 4'0000\nFinal init constraint equation: { \\b \\a } = 8'00000000\nImport proof-constraint: \\weak_ok = 1'1\nFinal proof equation: \\weak_ok = 1'1\nImport show expression: \\advance\nImport show expression: \\clk\nImport show expression: \\hidden\nImport show expression: \\strong_ok\nImport show expression: \\visible\nImport show expression: \\weak_ok\n\n[base case 1] Solving problem with 111 variables and 286 clauses..\nBase case for induction length 1 proven.\n\nSetting up time step 2:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport proof-constraint: \\weak_ok = 1'1\nFinal proof equation: \\weak_ok = 1'1\nImport show expression: \\advance\nImport show expression: \\clk\nImport show expression: \\hidden\nImport show expression: \\strong_ok\nImport show expression: \\visible\nImport show expression: \\weak_ok\n\n[induction step 1] Solving problem with 218 variables and 557 clauses..\nInduction step failed. Incrementing induction length.\n\n Time Signal Name Dec Hex Bin\n ---- --------------- ----------- --------- -------------\n init \\a 0 0 0000\n init \\b 14 e 1110\n ---- --------------- ----------- --------- -------------\n 1 \\advance 1 1 1\n 1 \\clk 0 0 0\n 1 \\hidden 14 e 1110\n 1 \\strong_ok 0 0 0\n 1 \\visible 0 0 0000\n 1 \\weak_ok 1 1 1\n ---- --------------- ----------- --------- -------------\n 2 \\advance 1 1 1\n 2 \\clk 0 0 0\n 2 \\hidden 15 f 1111\n 2 \\strong_ok 0 0 0\n 2 \\visible 14 e 1110\n 2 \\weak_ok 0 0 0\n\n** Trying induction with length 2 **\n\nSetting up time step 2:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport proof-constraint: \\weak_ok = 1'1\nFinal proof equation: \\weak_ok = 1'1\nImport show expression: \\advance\nImport show expression: \\clk\nImport show expression: \\hidden\nImport show expression: \\strong_ok\nImport show expression: \\visible\nImport show expression: \\weak_ok\n\n[base case 2] Solving problem with 257 variables and 689 clauses..\nBase case for induction length 2 proven.\n\nSetting up time step 3:\nFinal constraint equation: { } = { }\nImported 9 cells to SAT database.\nImport proof-constraint: \\weak_ok = 1'1\nFinal proof equation: \\weak_ok = 1'1\nImport show expression: \\advance\nImport show expression: \\clk\nImport show expression: \\hidden\nImport show expression: \\strong_ok\nImport show expression: \\visible\nImport show expression: \\weak_ok\n\n[induction step 2] Solving problem with 389 variables and 1042 clauses..\nInduction step proven: SUCCESS!\n\n /$$$$$$ /$$$$$$$$ /$$$$$$$ \n /$$__ $$ | $$_____/ | $$__ $$ \n | $$ \\ $$ | $$ | $$ \\ $$ \n | $$ | $$ | $$$$$ | $$ | $$ \n | $$ | $$ | $$__/ | $$ | $$ \n | $$/$$ $$ | $$ | $$ | $$ \n | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$\n \\____ $$$|__/|________/|__/|_______/|__/\n \\__/ \n\n", "stderr": "", "input_sha256": { "masked_bounded.ys": "bdf178d6f6c134c23ec056dfe99ad2095ba2b620a1f6f3b3034bd279a5688164", "strengthened_induction.ys": "c0f9849e3ed933ca38ff6a961adbbb08017f360266a684d29f70f61a6d627d11", "induction.sv": "31bfa2953dcfa67a352feb3bee5def35e0944c46caaf00326ee1a8dca4e486e6", "weak_induction.ys": "0c9564190e299dda044a38efa0dd59261d8f72b68d79147caf1e1cf04af960e2", "bounded_5.ys": "827a75335345d035df12c9d3ab0d1b06fcf6c79361bd3de5a7e64ad84cf7869d", "cover_unmasked.ys": "bcfcf94773673c7dde5237346acbcf416a5fa1821a308554c66b5dc9317de9a4", "deeper_6.ys": "b3e328858b39a400de7ebdff4170fb85843cb5746f307c628b8df66d4727a764", "masked_bug.sv": "44c0ab027ad89a94a5856227adcf4d4d01dffce43e634c8840fe68b31b3818c7", "cover_masked.ys": "7a78e789233cb208939ecb7267ac42a099e427c6179700ac6278774556a34bf9", "weak_induction_depth2.ys": "8b71caad233b5b514ba990032c06b6f7afdd0a042a76d484b660026554f56cfd", "late_bug.sv": "b2e71f3b573a9e6fb45ea383dca35c786c8c95492c84af8ed89a119acd8b2365" } } ], "earlier_record": "data/measurements/printed-hdl/earlier-p8/P15-yosys.json", "correction": "Temporal induction no longer uses -seq 1. P15 additionally demonstrates weak induction succeeding at length 2; P16 additionally checks its combinational contradiction at one arbitrary initial state.", "publication_omissions": "Routine elapsed-time and allocation summaries omitted; no performance claim. Absolute installation/build paths use portable tokens.", "preparation_failures": [ { "case": "masked_bounded", "started_at_utc": "2026-10-25T04:55:16.502984+00:00", "command": [ "yosys", "-Q", "-T", "-s", "masked_bounded.ys" ], "return_code": 1, "stdout": "\n-- Executing script file `masked_bounded.ys' --\n\n1. Executing Verilog-2005 frontend: masked_bug.sv\nParsing formal SystemVerilog input from `masked_bug.sv' to AST representation.\nGenerating RTLIL representation for module `\\masked_bug'.\nSuccessfully finished Verilog frontend.\n\n2. Executing PREP pass.\n\n2.1. Executing HIERARCHY pass (managing design hierarchy).\n\n2.1.1. Analyzing design hierarchy..\nTop module: \\masked_bug\n\n2.1.2. Analyzing design hierarchy..\nTop module: \\masked_bug\nRemoved 0 unused modules.\nModule masked_bug directly or indirectly contains formal properties -> setting \"keep\" attribute.\n\n2.2. Executing PROC pass (convert processes to netlists).\n\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nCleaned up 0 empty switches.\n\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nRemoved a total of 0 dead cases.\n\n2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 2 redundant assignments.\nPromoted 3 assignments to connections.\n\n2.2.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\masked_bug.$proc$masked_bug.sv:4$8'.\n Set init value: \\accepted = 3'000\n\n2.2.5. Executing PROC_ARST pass (detect async resets in processes).\n\n2.2.6. Executing PROC_ROM pass (convert switches to ROMs).\nConverted 0 switches.\n\n\n2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:4$8'.\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:8$4'.\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:5$1'.\n 1/1: $0\\accepted[2:0]\n\n2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).\n\n2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\masked_bug.\\accepted' using process `\\masked_bug.$proc$masked_bug.sv:5$1'.\n created $dff cell `$procdff$11' with positive edge clock.\n\n2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).\n\n2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `masked_bug.$proc$masked_bug.sv:4$8'.\nRemoving empty process `masked_bug.$proc$masked_bug.sv:8$4'.\nFound and cleaned up 1 empty switch in `\\masked_bug.$proc$masked_bug.sv:5$1'.\nRemoving empty process `masked_bug.$proc$masked_bug.sv:5$1'.\nCleaned up 1 empty switch.\n\n2.2.12. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.3. Executing FUTURE pass.\n\n2.4. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.5. Executing CHECK pass (checking for obvious problems).\nChecking module masked_bug...\nFound and reported 0 problems.\n\n2.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\nRemoved 0 unused cells and 6 unused wires.\n\n\n2.7. Executing OPT pass (performing simple optimizations).\n\n2.7.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.7.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\masked_bug..\n Creating internal representation of mux trees.\n Evaluating internal representation of mux trees.\n Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n\n\n2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\masked_bug.\nPerformed a total of 0 changes.\n\n2.7.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.7.7. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.7.8. Finished fast OPT passes. (There is nothing left to do.)\n\n2.8. Executing WREDUCE pass (reducing word size of cells).\nRemoved top 1 bits (of 3) from port B of cell masked_bug.$eq$masked_bug.sv:7$3 ($eq).\n\n2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.10. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n2.11. Executing OPT pass (performing simple optimizations).\n\n2.11.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.11.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.11.4. Finished fast OPT passes.\n\n2.12. Executing SORT pass.\n\n2.13. Printing statistics.\n\n=== masked_bug ===\n\n +----------Local Count, excluding submodules.\n | \n 8 wires\n 16 wire bits\n 5 public wires\n 9 public wire bits\n 4 ports\n 6 port bits\n 7 cells\n 1 $add\n 2 $check\n 1 $dff\n 1 $eq\n 1 $logic_not\n 1 $mux\n\n2.14. Executing CHECK pass (checking for obvious problems).\nChecking module masked_bug...\nFound and reported 0 problems.\n\n3. Executing SAT pass (solving SAT problems in the circuit).\nUsing SAT solver `minisat`.\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\n", "stderr": "ERROR: No SAT model available for cell $assume$masked_bug.sv:9$5 ($check).\n", "input_sha256": { "masked_bug.sv": "44c0ab027ad89a94a5856227adcf4d4d01dffce43e634c8840fe68b31b3818c7", "masked_bounded.ys": "e54205673857a6c25c34b030f1610d984acf74a988d635b163d88d1208e103ae" } }, { "case": "cover_masked", "started_at_utc": "2026-10-25T04:55:16.516228+00:00", "command": [ "yosys", "-Q", "-T", "-s", "cover_masked.ys" ], "return_code": 1, "stdout": "\n-- Executing script file `cover_masked.ys' --\n\n1. Executing Verilog-2005 frontend: masked_bug.sv\nParsing formal SystemVerilog input from `masked_bug.sv' to AST representation.\nGenerating RTLIL representation for module `\\masked_bug'.\nSuccessfully finished Verilog frontend.\n\n2. Executing PREP pass.\n\n2.1. Executing HIERARCHY pass (managing design hierarchy).\n\n2.1.1. Analyzing design hierarchy..\nTop module: \\masked_bug\n\n2.1.2. Analyzing design hierarchy..\nTop module: \\masked_bug\nRemoved 0 unused modules.\nModule masked_bug directly or indirectly contains formal properties -> setting \"keep\" attribute.\n\n2.2. Executing PROC pass (convert processes to netlists).\n\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nCleaned up 0 empty switches.\n\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nRemoved a total of 0 dead cases.\n\n2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 2 redundant assignments.\nPromoted 3 assignments to connections.\n\n2.2.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\masked_bug.$proc$masked_bug.sv:4$8'.\n Set init value: \\accepted = 3'000\n\n2.2.5. Executing PROC_ARST pass (detect async resets in processes).\n\n2.2.6. Executing PROC_ROM pass (convert switches to ROMs).\nConverted 0 switches.\n\n\n2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:4$8'.\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:8$4'.\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:5$1'.\n 1/1: $0\\accepted[2:0]\n\n2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).\n\n2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\masked_bug.\\accepted' using process `\\masked_bug.$proc$masked_bug.sv:5$1'.\n created $dff cell `$procdff$11' with positive edge clock.\n\n2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).\n\n2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `masked_bug.$proc$masked_bug.sv:4$8'.\nRemoving empty process `masked_bug.$proc$masked_bug.sv:8$4'.\nFound and cleaned up 1 empty switch in `\\masked_bug.$proc$masked_bug.sv:5$1'.\nRemoving empty process `masked_bug.$proc$masked_bug.sv:5$1'.\nCleaned up 1 empty switch.\n\n2.2.12. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.3. Executing FUTURE pass.\n\n2.4. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.5. Executing CHECK pass (checking for obvious problems).\nChecking module masked_bug...\nFound and reported 0 problems.\n\n2.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\nRemoved 0 unused cells and 6 unused wires.\n\n\n2.7. Executing OPT pass (performing simple optimizations).\n\n2.7.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.7.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\masked_bug..\n Creating internal representation of mux trees.\n Evaluating internal representation of mux trees.\n Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n\n\n2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\masked_bug.\nPerformed a total of 0 changes.\n\n2.7.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.7.7. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.7.8. Finished fast OPT passes. (There is nothing left to do.)\n\n2.8. Executing WREDUCE pass (reducing word size of cells).\nRemoved top 1 bits (of 3) from port B of cell masked_bug.$eq$masked_bug.sv:7$3 ($eq).\n\n2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.10. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n2.11. Executing OPT pass (performing simple optimizations).\n\n2.11.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.11.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.11.4. Finished fast OPT passes.\n\n2.12. Executing SORT pass.\n\n2.13. Printing statistics.\n\n=== masked_bug ===\n\n +----------Local Count, excluding submodules.\n | \n 8 wires\n 16 wire bits\n 5 public wires\n 9 public wire bits\n 4 ports\n 6 port bits\n 7 cells\n 1 $add\n 2 $check\n 1 $dff\n 1 $eq\n 1 $logic_not\n 1 $mux\n\n2.14. Executing CHECK pass (checking for obvious problems).\nChecking module masked_bug...\nFound and reported 0 problems.\n\n3. Executing SAT pass (solving SAT problems in the circuit).\nUsing SAT solver `minisat`.\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\n", "stderr": "ERROR: No SAT model available for cell $assume$masked_bug.sv:9$5 ($check).\n", "input_sha256": { "masked_bug.sv": "44c0ab027ad89a94a5856227adcf4d4d01dffce43e634c8840fe68b31b3818c7", "cover_masked.ys": "bd269e86113337ba30666ef0f979c9dbc1dba0d1b5be0621b5fd92690b4abb37" } }, { "case": "cover_unmasked", "started_at_utc": "2026-10-25T04:55:16.534198+00:00", "command": [ "yosys", "-Q", "-T", "-s", "cover_unmasked.ys" ], "return_code": 1, "stdout": "\n-- Executing script file `cover_unmasked.ys' --\n\n1. Executing Verilog-2005 frontend: masked_bug.sv\nParsing formal SystemVerilog input from `masked_bug.sv' to AST representation.\nGenerating RTLIL representation for module `\\masked_bug'.\nSuccessfully finished Verilog frontend.\n\n2. Executing PREP pass.\n\n2.1. Executing HIERARCHY pass (managing design hierarchy).\n\n2.1.1. Analyzing design hierarchy..\nTop module: \\masked_bug\n\n2.1.2. Analyzing design hierarchy..\nTop module: \\masked_bug\nRemoved 0 unused modules.\nModule masked_bug directly or indirectly contains formal properties -> setting \"keep\" attribute.\n\n2.2. Executing PROC pass (convert processes to netlists).\n\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nCleaned up 0 empty switches.\n\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nRemoved a total of 0 dead cases.\n\n2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 2 redundant assignments.\nPromoted 3 assignments to connections.\n\n2.2.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\masked_bug.$proc$masked_bug.sv:4$8'.\n Set init value: \\accepted = 3'000\n\n2.2.5. Executing PROC_ARST pass (detect async resets in processes).\n\n2.2.6. Executing PROC_ROM pass (convert switches to ROMs).\nConverted 0 switches.\n\n\n2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:4$8'.\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:8$4'.\nCreating decoders for process `\\masked_bug.$proc$masked_bug.sv:5$1'.\n 1/1: $0\\accepted[2:0]\n\n2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).\n\n2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\masked_bug.\\accepted' using process `\\masked_bug.$proc$masked_bug.sv:5$1'.\n created $dff cell `$procdff$11' with positive edge clock.\n\n2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).\n\n2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `masked_bug.$proc$masked_bug.sv:4$8'.\nRemoving empty process `masked_bug.$proc$masked_bug.sv:8$4'.\nFound and cleaned up 1 empty switch in `\\masked_bug.$proc$masked_bug.sv:5$1'.\nRemoving empty process `masked_bug.$proc$masked_bug.sv:5$1'.\nCleaned up 1 empty switch.\n\n2.2.12. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.3. Executing FUTURE pass.\n\n2.4. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.5. Executing CHECK pass (checking for obvious problems).\nChecking module masked_bug...\nFound and reported 0 problems.\n\n2.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\nRemoved 0 unused cells and 6 unused wires.\n\n\n2.7. Executing OPT pass (performing simple optimizations).\n\n2.7.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.7.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\masked_bug..\n Creating internal representation of mux trees.\n Evaluating internal representation of mux trees.\n Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n\n\n2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n Optimizing cells in module \\masked_bug.\nPerformed a total of 0 changes.\n\n2.7.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.7.7. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.7.8. Finished fast OPT passes. (There is nothing left to do.)\n\n2.8. Executing WREDUCE pass (reducing word size of cells).\nRemoved top 1 bits (of 3) from port B of cell masked_bug.$eq$masked_bug.sv:7$3 ($eq).\n\n2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.10. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n2.11. Executing OPT pass (performing simple optimizations).\n\n2.11.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module masked_bug.\n\n2.11.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\masked_bug'.\nComputing hashes of 7 cells of `\\masked_bug'.\nFinding duplicate cells in `\\masked_bug'.\nRemoved a total of 0 cells.\n\n2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\masked_bug..\n\n2.11.4. Finished fast OPT passes.\n\n2.12. Executing SORT pass.\n\n2.13. Printing statistics.\n\n=== masked_bug ===\n\n +----------Local Count, excluding submodules.\n | \n 8 wires\n 16 wire bits\n 5 public wires\n 9 public wire bits\n 4 ports\n 6 port bits\n 7 cells\n 1 $add\n 2 $check\n 1 $dff\n 1 $eq\n 1 $logic_not\n 1 $mux\n\n2.14. Executing CHECK pass (checking for obvious problems).\nChecking module masked_bug...\nFound and reported 0 problems.\n\n3. Executing SAT pass (solving SAT problems in the circuit).\nUsing SAT solver `minisat`.\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\n", "stderr": "ERROR: No SAT model available for cell $assume$masked_bug.sv:9$5 ($check).\n", "input_sha256": { "masked_bug.sv": "44c0ab027ad89a94a5856227adcf4d4d01dffce43e634c8840fe68b31b3818c7", "cover_unmasked.ys": "81ab93c15da32472566a632811982041107d7c5d2854810c32375744b295d6f9" } } ], "preparation_failure_resolution": "The HDL was retained. Adding documented chformal -lower converted $check assumptions into SAT-supported assumption cells. The final scripts also contain an MIT licence comment." }