{
  "page_id": "P16",
  "recorded_at_utc": "2026-10-25T14:29:51.906739+00:00",
  "provenance": {
    "tool": "Yosys",
    "version": "0.70+post",
    "release_tag": "v0.70",
    "release_tag_commit": "28ba3cb926fe376fa05ebfc1b921747d011d4557",
    "release_tag_url": "https://github.com/YosysHQ/yosys/releases/tag/v0.70",
    "binary_reported_revision": "0c11ea098be065e585a90a06e7b7da49936cf231",
    "binary_version_output": "Yosys 0.70+post (git sha1 0c11ea098be065e585a90a06e7b7da49936cf231, Release, AppleClang clang++ 21.0.0.21000334)",
    "binary_sha256": "aff1882664d6775739a1d99d086e054dc71ca6d22d2a6d0d3ee6f3e382fa0daf",
    "revision_note": "The binary reports 0.70+post and the revision above. That revision is not the official v0.70 tag commit. The binary source build was not independently reconstructed.",
    "os": "macOS 27.0.1",
    "architecture": "arm64"
  },
  "cases": [
    {
      "case": "unreachable",
      "started_at_utc": "2026-10-25T14:29:51.885230+00:00",
      "ended_at_utc": "2026-10-25T14:29:51.895161+00:00",
      "command": [
        "${TOOL_WORKSPACE}/runtime/formal-tools/cellar/yosys/0.70/bin/yosys",
        "-Q",
        "-T",
        "-s",
        "unreachable.ys"
      ],
      "return_code": 0,
      "stdout": "\n-- Executing script file `unreachable.ys' --\n\n1. Executing Verilog-2005 frontend: design.sv\nParsing formal SystemVerilog input from `design.sv' to AST representation.\nGenerating RTLIL representation for module `\\packet_gate'.\nSuccessfully finished Verilog frontend.\n\n2. Executing PREP pass.\n\n2.1. Executing HIERARCHY pass (managing design hierarchy).\n\n2.1.1. Analyzing design hierarchy..\nTop module:  \\packet_gate\n\n2.1.2. Analyzing design hierarchy..\nTop module:  \\packet_gate\nRemoved 0 unused modules.\n\n2.2. Executing PROC pass (convert processes to netlists).\n\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nCleaned up 0 empty switches.\n\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nMarked 2 switch rules as full_case in process $proc$design.sv:15$10 in module packet_gate.\nRemoved a total of 0 dead cases.\n\n2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 0 redundant assignments.\nPromoted 1 assignment to connection.\n\n2.2.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\packet_gate.$proc$design.sv:8$19'.\n  Set init value: \\used = 2'00\n\n2.2.5. Executing PROC_ARST pass (detect async resets in processes).\n\n2.2.6. Executing PROC_ROM pass (convert switches to ROMs).\nConverted 0 switches.\n<suppressed ~3 debug messages>\n\n2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\packet_gate.$proc$design.sv:8$19'.\nCreating decoders for process `\\packet_gate.$proc$design.sv:15$10'.\n     1/1: $0\\used[1:0]\n\n2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).\n\n2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\packet_gate.\\used' using process `\\packet_gate.$proc$design.sv:15$10'.\n  created $dff cell `$procdff$28' with positive edge clock.\n\n2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).\n\n2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `packet_gate.$proc$design.sv:8$19'.\nFound and cleaned up 3 empty switches in `\\packet_gate.$proc$design.sv:15$10'.\nRemoving empty process `packet_gate.$proc$design.sv:15$10'.\nCleaned up 3 empty switches.\n\n2.2.12. Executing OPT_EXPR pass (perform const folding).\nOptimizing module packet_gate.\n<suppressed ~2 debug messages>\n\n2.3. Executing FUTURE pass.\n\n2.4. Executing OPT_EXPR pass (perform const folding).\nOptimizing module packet_gate.\n\n2.5. Executing CHECK pass (checking for obvious problems).\nChecking module packet_gate...\nFound and reported 0 problems.\n\n2.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\packet_gate..\nRemoved 0 unused cells and 10 unused wires.\n<suppressed ~1 debug messages>\n\n2.7. Executing OPT pass (performing simple optimizations).\n\n2.7.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module packet_gate.\n\n2.7.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\packet_gate'.\nComputing hashes of 21 cells of `\\packet_gate'.\nFinding duplicate cells in `\\packet_gate'.\nRemoved a total of 0 cells.\n\n2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\packet_gate..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~4 debug messages>\n\n2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\packet_gate.\nPerformed a total of 0 changes.\n\n2.7.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\packet_gate'.\nComputing hashes of 21 cells of `\\packet_gate'.\nFinding duplicate cells in `\\packet_gate'.\nRemoved a total of 0 cells.\n\n2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\packet_gate..\n\n2.7.7. Executing OPT_EXPR pass (perform const folding).\nOptimizing module packet_gate.\n\n2.7.8. Finished fast OPT passes. (There is nothing left to do.)\n\n2.8. Executing WREDUCE pass (reducing word size of cells).\n\n2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\packet_gate..\n\n2.10. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n2.11. Executing OPT pass (performing simple optimizations).\n\n2.11.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module packet_gate.\n\n2.11.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\packet_gate'.\nComputing hashes of 21 cells of `\\packet_gate'.\nFinding duplicate cells in `\\packet_gate'.\nRemoved a total of 0 cells.\n\n2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\packet_gate..\n\n2.11.4. Finished fast OPT passes.\n\n2.12. Executing SORT pass.\n\n2.13. Printing statistics.\n\n=== packet_gate ===\n\n        +----------Local Count, excluding submodules.\n        | \n       28 wires\n       38 wire bits\n       13 public wires\n       18 public wire bits\n       12 ports\n       16 port bits\n       21 cells\n        1   $add\n        1   $dff\n        1   $eq\n        8   $logic_and\n        5   $logic_not\n        3   $mux\n        1   $reduce_bool\n        1   $sub\n\n2.14. Executing CHECK pass (checking for obvious problems).\nChecking module packet_gate...\nFound and reported 0 problems.\n\n3. Executing SAT pass (solving SAT problems in the circuit).\nUsing SAT solver `minisat`.\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 21 cells to SAT database.\nImport proof-constraint: \\impossible = 1'0\nFinal proof equation: \\impossible = 1'0\n\n** Trying induction with length 1 **\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 21 cells to SAT database.\nImport set-constraint from init attribute: \\used = 2'00\nFinal init constraint equation: \\used = 2'00\nImport proof-constraint: \\impossible = 1'0\nFinal proof equation: \\impossible = 1'0\nImport show expression: \\clk\nImport show expression: \\debug_request\nImport show expression: \\length\nImport show expression: \\release_slot\nImport show expression: \\request\nImport show expression: \\reset\nImport show expression: \\accepted\nImport show expression: \\debug_accepted\nImport show expression: \\empty\nImport show expression: \\full\nImport show expression: \\impossible\nImport show expression: \\occupancy\n\n[base case 1] Solving problem with 156 variables and 386 clauses..\nBase case for induction length 1 proven.\n\nSetting up time step 2:\nFinal constraint equation: { } = { }\nImported 21 cells to SAT database.\nImport proof-constraint: \\impossible = 1'0\nFinal proof equation: \\impossible = 1'0\nImport show expression: \\clk\nImport show expression: \\debug_request\nImport show expression: \\length\nImport show expression: \\release_slot\nImport show expression: \\request\nImport show expression: \\reset\nImport show expression: \\accepted\nImport show expression: \\debug_accepted\nImport show expression: \\empty\nImport show expression: \\full\nImport show expression: \\impossible\nImport show expression: \\occupancy\n\n[induction step 1] Solving problem with 312 variables and 775 clauses..\nInduction step proven: SUCCESS!\n\n                  /$$$$$$      /$$$$$$$$     /$$$$$$$    \n                 /$$__  $$    | $$_____/    | $$__  $$   \n                | $$  \\ $$    | $$          | $$  \\ $$   \n                | $$  | $$    | $$$$$       | $$  | $$   \n                | $$  | $$    | $$__/       | $$  | $$   \n                | $$/$$ $$    | $$          | $$  | $$   \n                |  $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$\n                 \\____ $$$|__/|________/|__/|_______/|__/\n                       \\__/                              \n\n",
      "stderr": "",
      "input_sha256": {
        "contradiction_any_state.ys": "bd1b49330f097fc8cbfde2f8b12d1604d3976a23cf671f1ce77fee63d5821c34",
        "testbench.sv": "6dd0250fa756f23efb9fdf71bd90298ebb9f1489d8c42a2d0028dfa266e71b5d",
        "design.sv": "5312cadb0398962b943ab5c7ef3a6274ca627f13fa5804d6b9c9e1322a87424d",
        "unreachable.ys": "96b75433184c1a703274f5039086a60bdbf6e1e9913e2c7d4c859d8bc852af2f"
      }
    },
    {
      "case": "contradiction_any_state",
      "started_at_utc": "2026-10-25T14:29:51.896683+00:00",
      "ended_at_utc": "2026-10-25T14:29:51.905880+00:00",
      "command": [
        "${TOOL_WORKSPACE}/runtime/formal-tools/cellar/yosys/0.70/bin/yosys",
        "-Q",
        "-T",
        "-s",
        "contradiction_any_state.ys"
      ],
      "return_code": 0,
      "stdout": "\n-- Executing script file `contradiction_any_state.ys' --\n\n1. Executing Verilog-2005 frontend: design.sv\nParsing formal SystemVerilog input from `design.sv' to AST representation.\nGenerating RTLIL representation for module `\\packet_gate'.\nSuccessfully finished Verilog frontend.\n\n2. Executing PREP pass.\n\n2.1. Executing HIERARCHY pass (managing design hierarchy).\n\n2.1.1. Analyzing design hierarchy..\nTop module:  \\packet_gate\n\n2.1.2. Analyzing design hierarchy..\nTop module:  \\packet_gate\nRemoved 0 unused modules.\n\n2.2. Executing PROC pass (convert processes to netlists).\n\n2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nCleaned up 0 empty switches.\n\n2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\nMarked 2 switch rules as full_case in process $proc$design.sv:15$10 in module packet_gate.\nRemoved a total of 0 dead cases.\n\n2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\nRemoved 0 redundant assignments.\nPromoted 1 assignment to connection.\n\n2.2.4. Executing PROC_INIT pass (extract init attributes).\nFound init rule in `\\packet_gate.$proc$design.sv:8$19'.\n  Set init value: \\used = 2'00\n\n2.2.5. Executing PROC_ARST pass (detect async resets in processes).\n\n2.2.6. Executing PROC_ROM pass (convert switches to ROMs).\nConverted 0 switches.\n<suppressed ~3 debug messages>\n\n2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).\nCreating decoders for process `\\packet_gate.$proc$design.sv:8$19'.\nCreating decoders for process `\\packet_gate.$proc$design.sv:15$10'.\n     1/1: $0\\used[1:0]\n\n2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).\n\n2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).\nCreating register for signal `\\packet_gate.\\used' using process `\\packet_gate.$proc$design.sv:15$10'.\n  created $dff cell `$procdff$28' with positive edge clock.\n\n2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).\n\n2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).\nRemoving empty process `packet_gate.$proc$design.sv:8$19'.\nFound and cleaned up 3 empty switches in `\\packet_gate.$proc$design.sv:15$10'.\nRemoving empty process `packet_gate.$proc$design.sv:15$10'.\nCleaned up 3 empty switches.\n\n2.2.12. Executing OPT_EXPR pass (perform const folding).\nOptimizing module packet_gate.\n<suppressed ~2 debug messages>\n\n2.3. Executing FUTURE pass.\n\n2.4. Executing OPT_EXPR pass (perform const folding).\nOptimizing module packet_gate.\n\n2.5. Executing CHECK pass (checking for obvious problems).\nChecking module packet_gate...\nFound and reported 0 problems.\n\n2.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\packet_gate..\nRemoved 0 unused cells and 10 unused wires.\n<suppressed ~1 debug messages>\n\n2.7. Executing OPT pass (performing simple optimizations).\n\n2.7.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module packet_gate.\n\n2.7.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\packet_gate'.\nComputing hashes of 21 cells of `\\packet_gate'.\nFinding duplicate cells in `\\packet_gate'.\nRemoved a total of 0 cells.\n\n2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\nRunning muxtree optimizer on module \\packet_gate..\n  Creating internal representation of mux trees.\n  Evaluating internal representation of mux trees.\n  Analyzing evaluation results.\nRemoved 0 multiplexer ports.\n<suppressed ~4 debug messages>\n\n2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n  Optimizing cells in module \\packet_gate.\nPerformed a total of 0 changes.\n\n2.7.5. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\packet_gate'.\nComputing hashes of 21 cells of `\\packet_gate'.\nFinding duplicate cells in `\\packet_gate'.\nRemoved a total of 0 cells.\n\n2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\packet_gate..\n\n2.7.7. Executing OPT_EXPR pass (perform const folding).\nOptimizing module packet_gate.\n\n2.7.8. Finished fast OPT passes. (There is nothing left to do.)\n\n2.8. Executing WREDUCE pass (reducing word size of cells).\n\n2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\packet_gate..\n\n2.10. Executing MEMORY_COLLECT pass (generating $mem cells).\n\n2.11. Executing OPT pass (performing simple optimizations).\n\n2.11.1. Executing OPT_EXPR pass (perform const folding).\nOptimizing module packet_gate.\n\n2.11.2. Executing OPT_MERGE pass (detect identical cells).\nFinding identical cells in module `\\packet_gate'.\nComputing hashes of 21 cells of `\\packet_gate'.\nFinding duplicate cells in `\\packet_gate'.\nRemoved a total of 0 cells.\n\n2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).\nFinding unused cells or wires in module \\packet_gate..\n\n2.11.4. Finished fast OPT passes.\n\n2.12. Executing SORT pass.\n\n2.13. Printing statistics.\n\n=== packet_gate ===\n\n        +----------Local Count, excluding submodules.\n        | \n       28 wires\n       38 wire bits\n       13 public wires\n       18 public wire bits\n       12 ports\n       16 port bits\n       21 cells\n        1   $add\n        1   $dff\n        1   $eq\n        8   $logic_and\n        5   $logic_not\n        3   $mux\n        1   $reduce_bool\n        1   $sub\n\n2.14. Executing CHECK pass (checking for obvious problems).\nChecking module packet_gate...\nFound and reported 0 problems.\n\n3. Executing SAT pass (solving SAT problems in the circuit).\nUsing SAT solver `minisat`.\n\nSetting up time step 1:\nFinal constraint equation: { } = { }\nImported 21 cells to SAT database.\nNo constraints for initial state found.\n\nImport proof-constraint: \\impossible = 1'0\nFinal proof equation: \\impossible = 1'0\nImport show expression: \\clk\nImport show expression: \\debug_request\nImport show expression: \\length\nImport show expression: \\release_slot\nImport show expression: \\request\nImport show expression: \\reset\nImport show expression: \\accepted\nImport show expression: \\debug_accepted\nImport show expression: \\empty\nImport show expression: \\full\nImport show expression: \\impossible\nImport show expression: \\occupancy\n\nSolving problem with 155 variables and 382 clauses..\nSAT proof finished - no model found: SUCCESS!\n\n                  /$$$$$$      /$$$$$$$$     /$$$$$$$    \n                 /$$__  $$    | $$_____/    | $$__  $$   \n                | $$  \\ $$    | $$          | $$  \\ $$   \n                | $$  | $$    | $$$$$       | $$  | $$   \n                | $$  | $$    | $$__/       | $$  | $$   \n                | $$/$$ $$    | $$          | $$  | $$   \n                |  $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$\n                 \\____ $$$|__/|________/|__/|_______/|__/\n                       \\__/                              \n\n",
      "stderr": "",
      "input_sha256": {
        "contradiction_any_state.ys": "bd1b49330f097fc8cbfde2f8b12d1604d3976a23cf671f1ce77fee63d5821c34",
        "testbench.sv": "6dd0250fa756f23efb9fdf71bd90298ebb9f1489d8c42a2d0028dfa266e71b5d",
        "design.sv": "5312cadb0398962b943ab5c7ef3a6274ca627f13fa5804d6b9c9e1322a87424d",
        "unreachable.ys": "96b75433184c1a703274f5039086a60bdbf6e1e9913e2c7d4c859d8bc852af2f"
      }
    }
  ],
  "earlier_record": "data/measurements/printed-hdl/earlier-p8/P16-yosys.json",
  "correction": "Temporal induction no longer uses -seq 1. P15 additionally demonstrates weak induction succeeding at length 2; P16 additionally checks its combinational contradiction at one arbitrary initial state.",
  "publication_omissions": "Routine elapsed-time and allocation summaries omitted; no performance claim. Absolute installation/build paths use portable tokens.",
  "preparation_failures": [
    {
      "command_text": "read_verilog -formal -sv design.sv; prep -top packet_gate; setattr -unset init w:used; sat -seq 1 -set-init-def -prove impossible 0 -show-ports",
      "return_code": 1,
      "stderr": "ERROR: Assert `!undef_mode || model_undef' failed in kernel/satgen.h:93.\n",
      "result": "No proof result; the final arbitrary-state command removes -set-init-def and leaves the initial state unconstrained in the default two-state SAT model."
    }
  ]
}