chipdesignmag.com ยท ORIGINAL EVIDENCE
EDA tool handoff evidence
Documented capabilities across twenty open-source tools. These rows are not measurements of cross-tool compatibility.
20 of 20 records
| Tool | Stage | Inputs | Outputs | Licence | Version record |
|---|---|---|---|---|---|
| Yosys | RTL synthesis | Verilog and synthesizable SystemVerilog subset | Synthesized Verilog netlist in documented example | ISC core; ABC and libraries have separate licences | Pinned repository commit; not claimed latest release |
| Verilator | RTL simulation and lint | Verilog/SystemVerilog | C++/header models, SystemC and JSON | LGPL-3.0-only OR Artistic-2.0 project declaration | Pinned repository commit; not claimed latest release |
| cocotb | Python-driven HDL verification | Python with Verilog/VHDL design sources | Not verified | BSD-3-Clause root licence | Pinned repository commit plus dated stable documentation |
| SBY | Formal verification orchestration | HDL plus .sby configuration | Task logs, status and counterexample trace artifacts | ISC; proof engines have separate licences | Pinned repository commit plus dated documentation |
| Surelog | SystemVerilog front end | SystemVerilog | UHDM serialized design model | Apache-2.0 root licence | Pinned repository commit |
| Icarus Verilog | HDL compilation and simulation | Verilog | Not verified | GPLv2 text in COPYING; per-file exceptions not fully inventoried | Pinned repository commit; distinct from D3 installed simulator version |
| GHDL | VHDL simulation; experimental synthesis | VHDL | Waveforms; experimental VHDL-1993 synthesized netlist | GPLv2 code; documentation separately licensed | Pinned repository commit |
| NVC | VHDL simulation | VHDL; experimental Verilog | FST waveform in documented example | GPL-3.0-or-later core; specified VHDL libraries Apache-2.0 | Pinned repository commit |
| Verible | SystemVerilog parsing, lint and formatting | SystemVerilog | Concrete syntax tree JSON and formatted source | Apache-2.0 with file-specific third-party notices | Pinned repository commit |
| slang | SystemVerilog language front end | SystemVerilog | AST JSON and API model | MIT | Pinned repository commit |
| sv2v | HDL conversion | SystemVerilog | Verilog source to stdout or files | BSD-3-Clause | Pinned repository commit |
| UHDM | Design representation and interchange | SystemVerilog object-model definitions | Persisted UHDM models and C++/VPI API access | Apache-2.0 | Pinned repository commit |
| OpenROAD | ASIC physical design | Verilog netlist plus physical/timing inputs | Physical-design handoff within ORFS; GDSII generation uses KLayout | BSD-3-Clause; PDKs and other tools separately licensed | Pinned repository commit |
| OpenSTA | Static timing analysis | Gate-level Verilog and timing constraints | Timing reports through Tcl commands | GPL-3.0 open-source option; separate commercial licence exists | Pinned repository commit |
| KLayout | Layout viewing/editing and checking | Layout databases; Ruby/Python scripting | GDSII/OASIS read/write | Project introduction: GPL-2.0-or-later; repository supplies GPLv3 text | Pinned repository commit plus dated project introduction |
| Magic | Layout editing, extraction and DRC | Not verified | GDS/CIF and hierarchical SPICE extraction documented | University of California permissive notice in LICENSE | Pinned repository commit |
| Netgen | Netlist comparison / LVS | Not verified | Netlist conversions and comparison report | Copying contains GPLv1 text; complete current per-file scope unverified | Pinned repository commit |
| nextpnr | FPGA place and route | Not verified | iCE40 ASC in documented example; outputs vary by architecture | ISC | Pinned repository commit |
| FuseSoC | HDL package and build orchestration | HDL sources and package metadata | Backend-specific simulation/build products | BSD-2-Clause | Pinned repository commit plus stable documentation snapshot |
| ngspice | Analog/mixed-signal circuit simulation | SPICE netlists and device/model descriptions | Simulation data, voltage/current results and plots | Modified BSD for most code, with exceptions explicitly retained | Official manual 47+ development edition, September 28, 2026; source revision not pinned |
No records match these filters. Reset to see the full audited set.
Unknown means not verified in this audit. Original compilation: CC BY 4.0. Upstream projects retain their own licences. No ranking or compatibility certification is implied.