chipdesignmag.com ยท ORIGINAL EVIDENCE
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20 of 20 records
| Core | Interface | Licence | Language | Verified collateral | Commit |
|---|---|---|---|---|---|
| Ibex | Native request/grant | Apache-2.0 | SystemVerilog | Register description; Software collateral; Build manifest; Formal collateral; Integration example | a896ef22777a |
| PicoRV32 | Native memory; AXI4-Lite; Wishbone | ISC | Verilog | Register description; Software collateral; Build manifest; Simulation testbench; Formal collateral; Timing constraints; Integration example | ef203c2b0a3f |
| NEORV32 | Wishbone; AXI4 bridge | BSD-3-Clause | VHDL | Register description; Software collateral; Simulation testbench; Integration example | 7d48364855ca |
| PULP AXI | AXI4; AXI4-Lite; AXI5 ATOP | SHL-0.51 / Apache-2.0 option | SystemVerilog | Register description; Build manifest; Simulation testbench; Integration example | 70b8e54fd460 |
| LiteEth | Wishbone; AXI4-Lite; Etherbone; AXI-Stream adapter | BSD-2-Clause | Python; Generated Verilog | Register description; Build manifest; Simulation testbench; Integration example | cc9a53054bc3 |
| CV32E40P | Native instruction/data | SHL-0.51 / Apache-2.0 option | SystemVerilog | Register description; Build manifest; Simulation testbench; Formal collateral; Timing constraints | b353438ff469 |
| VexRiscv | AXI4; Avalon; Wishbone | MIT | Scala; Generated Verilog | Register description; Build manifest; Simulation testbench; Integration example | baf7dc82f855 |
| Microwatt | Wishbone | CC-BY-4.0; additional rights caveat | VHDL | Build manifest; Simulation testbench; Timing constraints; Integration example | f341bed306a9 |
| ZipCPU | Wishbone; AXI4-Lite; AXI4 | GPL-3.0 | Verilog | Register description; Software collateral; Build manifest; Formal collateral | 42606d2d6ef5 |
| SERV | Native request/acknowledge | ISC | Verilog | Register description; Software collateral; Build manifest; Simulation testbench; Timing constraints; Integration example | f200eb2ed7b6 |
| Rocket Chip | TileLink; AXI4; AHB-Lite; APB | BSD-3-Clause / Apache-2.0 scopes | Scala; Generated RTL | Register description; Build manifest; Simulation testbench; Integration example | ece7b9ad544b |
| OpenTitan AES | TL-UL | Apache-2.0 | SystemVerilog | Register description; Software collateral; Build manifest; Simulation testbench; Formal collateral | 478afb033bb2 |
| OpenTitan HMAC | TL-UL | Apache-2.0 | SystemVerilog | Register description; Software collateral; Build manifest; Simulation testbench; Formal collateral | 478afb033bb2 |
| Caliptra SHA-512 | AHB-Lite; Native memory-like | Apache-2.0 / BSD-2-Clause scopes | SystemVerilog | Register description; Build manifest; Simulation testbench; Formal collateral | 5e577ee820ff |
| PULP APB I2C | APB; I2C | Partial licence evidence | SystemVerilog | Register description; Build manifest | 84855413cc2c |
| wb2axip | Wishbone; AXI4; AXI4-Lite; AHB; APB | Apache-2.0 | Verilog | Register description; Build manifest; Formal collateral | 2e8d3bc2d26d |
| LiteSPI | Wishbone; CSR; SPI | BSD-2-Clause | Python; Generated RTL | Register description; Build manifest; Simulation testbench | 1efda7b0ffe4 |
| LiteSDCard | CSR; LiteX stream; SD | BSD-2-Clause | Python; Generated RTL | Register description; Build manifest; Simulation testbench; Integration example | b68dfded8a76 |
| verilog-ethernet | AXI-Stream; MII; GMII; XGMII | MIT | Verilog | Simulation testbench; Timing constraints; Integration example | 77320a9471d1 |
| verilog-axi | AXI4; AXI4-Lite | MIT | Verilog | Register description; Build manifest; Simulation testbench | 516bd5dadc33 |
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Unknown means not verified in this audit. Original compilation: CC BY 4.0. Upstream projects retain their own licences. No ranking or compatibility certification is implied.