chipdesignmag.com · ORIGINAL EVIDENCE
HDL simulator observations
Thirty original deterministic examples in Icarus Verilog 13.0 and Verilator 5.052. Differences describe these configurations, not conformance verdicts.
30 of 30 records
| Example | Category | Icarus OBS output | Verilator OBS output | Payload |
|---|---|---|---|---|
| F01 · Explicit unknown assignment | four-state | OBS value=10x1 unknown=1 | OBS value=1001 unknown=0 | Different |
| F02 · Uninitialized register | initialization | OBS value=xxxxxxxx unknown=1 | OBS value=00000000 unknown=0 | Different |
| F03 · Mixed signed comparison | signedness | OBS mixed_less=0 cast_less=1 | OBS mixed_less=0 cast_less=1 | Same |
| F04 · Assignment-width truncation | width | OBS narrow=1 wide=17 | OBS narrow=1 wide=17 | Same |
| F05 · Clocked nonblocking update | ordering | OBS a=1 b=0 | OBS a=1 b=0 | Same |
| F06 · Signed extension | signedness | OBS a=-8 b=-8 bits=fff8 | OBS a=-8 b=-8 bits=fff8 | Same |
| F07 · Unsigned extension | signedness | OBS a=248 b=248 bits=00f8 | OBS a=248 b=248 bits=00f8 | Same |
| F08 · Logical and arithmetic shifts | signedness | OBS logical=3c arithmetic=fc | OBS logical=3c arithmetic=fc | Same |
| F09 · Unsized literal widths | width | OBS decimal_bits=32 hex_bits=32 value=1 | OBS decimal_bits=32 hex_bits=32 value=1 | Same |
| F10 · Expression assignment context | width | OBS narrow=0 wide=16 | OBS narrow=0 wide=16 | Same |
| F11 · Concatenation unsigned comparison | signedness | OBS signed_less=1 concat_less=0 | OBS signed_less=1 concat_less=0 | Same |
| F12 · Explicit signed cast | signedness | OBS unsigned=255 signed=-1 | OBS unsigned=255 signed=-1 | Same |
| F13 · Unknown condition in if | four-state | OBS sel=x branch=2 | OBS sel=0 branch=2 | Different |
| F14 · Unknown conditional bit merge | four-state | OBS value=10xx | OBS value=1001 | Different |
| F15 · Case equality against unknown | four-state | OBS ordinary=x case_x=1 unknown=1 | OBS ordinary=1 case_x=0 unknown=0 | Different |
| F16 · Reduction with unknown bit | four-state | OBS and=x or=1 xor=x | OBS and=0 or=1 xor=1 | Different |
| F17 · Controlling bitwise zero | four-state | OBS x_and_0=0 x_or_1=1 | OBS x_and_0=0 x_or_1=1 | Same |
| F18 · Unknown XOR operand | four-state | OBS x_xor_0=x | OBS x_xor_0=0 | Different |
| F19 · Two-state bit assignment | four-state | OBS bit=0 logic=x | OBS bit=0 logic=0 | Different |
| F20 · Explicit register initialization | initialization | OBS value=5a | OBS value=5a | Same |
| F21 · Declaration initialization | initialization | OBS value=a5 | OBS value=a5 | Same |
| F22 · Blocking statements in one process | ordering | OBS a=2 b=2 | OBS a=2 b=2 | Same |
| F23 · Nonblocking swap after edge | ordering | OBS a=2 b=1 | OBS a=2 b=1 | Same |
| F24 · Last nonblocking assignment in process | ordering | OBS a=2 | OBS a=2 | Same |
| F25 · Three-stage pipeline | ordering | OBS a=1 b=0 c=0; OBS a=2 b=1 c=0; OBS a=3 b=2 c=1 | OBS a=1 b=0 c=0; OBS a=2 b=1 c=0; OBS a=3 b=2 c=1 | Same |
| F26 · Opposite-edge stimulus | ordering | OBS d=1 q=1 | OBS d=1 q=1 | Same |
| F27 · Asynchronous reset then clock | initialization | OBS reset_q=0; OBS clock_q=1 | OBS reset_q=0; OBS clock_q=1 | Same |
| F28 · Explicit modulo arithmetic sequence | seed | OBS state=3d20bdba; OBS state=e9dab1d1; OBS state=9ccc40fc | OBS state=3d20bdba; OBS state=e9dab1d1; OBS state=9ccc40fc | Same |
| F29 · Seeded random sequence | seed | OBS random=8011ec00 seed=0011ea9e; OBS random=61e0e9c3 seed=e1e0e687; OBS random=b3547666 seed=3354751c | OBS random=979a27f1 seed=a79f332a; OBS random=7d04cbad seed=83d6c4a7; OBS random=9c22637a seed=0e23cf8b | Different |
| F30 · Seeded urandom process | seed | OBS urandom=0011ec00; OBS urandom=e1e0e9c3; OBS urandom=33547666 | OBS urandom=a79f332a; OBS urandom=979a27f1; OBS urandom=b38d6fdb | Different |
No records match these filters. Reset to see the full audited set.
Unknown means not verified in this audit. Original compilation: CC BY 4.0. Upstream projects retain their own licences. No ranking or compatibility certification is implied.