Compare open IP integration evidence
Compare open IP by the integration evidence available at a pinned revision: clock and reset behavior, interfaces, register descriptions, software, constraints and verification collateral. A repository containing a testbench or driver provides something to inspect, not proof that the core works in your system. Unknown fields below mean this audit did not verify the item at the selected revision.
Begin with the boundary your system must satisfy
Write down the required interface and operating assumptions before comparing rows. An interface name alone leaves timing, widths, parameter choices and optional behavior unresolved. A core that appears suitable from its README may still need an adapter, different reset handling or additional checks at the surrounding system boundary.
The twenty records below use pinned commits and source paths from the cores’ own repositories. Some records share a repository or project family; they are distinct core records, not twenty independent maintenance organizations. The snapshot identifies what was located during this audit rather than estimating each project’s support capacity.
| Core | Interfaces | Language | Licence scope | Located collateral | Commit |
|---|---|---|---|---|---|
| Ibex1 | Native request/grant | SystemVerilog | Apache-2.0 | Register description; Software collateral; Build manifest; Formal collateral; Integration example | a896ef22777a |
| PicoRV322 | Native memory; AXI4-Lite; Wishbone | Verilog | ISC | Register description; Software collateral; Build manifest; Simulation testbench; Formal collateral; Timing constraints; Integration example | ef203c2b0a3f |
| NEORV323 | Wishbone; AXI4 bridge | VHDL | BSD-3-Clause | Register description; Software collateral; Simulation testbench; Integration example | 7d48364855ca |
| PULP AXI4 | AXI4; AXI4-Lite; AXI5 ATOP | SystemVerilog | SHL-0.51 / Apache-2.0 option | Register description; Build manifest; Simulation testbench; Integration example | 70b8e54fd460 |
| LiteEth5 | Wishbone; AXI4-Lite; Etherbone; AXI-Stream adapter | Python; Generated Verilog | BSD-2-Clause | Register description; Build manifest; Simulation testbench; Integration example | cc9a53054bc3 |
| CV32E40P6 | Native instruction/data | SystemVerilog | SHL-0.51 / Apache-2.0 option | Register description; Build manifest; Simulation testbench; Formal collateral; Timing constraints | b353438ff469 |
| VexRiscv7 | AXI4; Avalon; Wishbone | Scala; Generated Verilog | MIT | Register description; Build manifest; Simulation testbench; Integration example | baf7dc82f855 |
| Microwatt8 | Wishbone | VHDL | CC-BY-4.0; additional rights caveat | Build manifest; Simulation testbench; Timing constraints; Integration example | f341bed306a9 |
| ZipCPU9 | Wishbone; AXI4-Lite; AXI4 | Verilog | GPL-3.0 | Register description; Software collateral; Build manifest; Formal collateral | 42606d2d6ef5 |
| SERV10 | Native request/acknowledge | Verilog | ISC | Register description; Software collateral; Build manifest; Simulation testbench; Timing constraints; Integration example | f200eb2ed7b6 |
| Rocket Chip11 | TileLink; AXI4; AHB-Lite; APB | Scala; Generated RTL | BSD-3-Clause / Apache-2.0 scopes | Register description; Build manifest; Simulation testbench; Integration example | ece7b9ad544b |
| OpenTitan AES12 | TL-UL | SystemVerilog | Apache-2.0 | Register description; Software collateral; Build manifest; Simulation testbench; Formal collateral | 478afb033bb2 |
| OpenTitan HMAC13 | TL-UL | SystemVerilog | Apache-2.0 | Register description; Software collateral; Build manifest; Simulation testbench; Formal collateral | 478afb033bb2 |
| Caliptra SHA-51214 | AHB-Lite; Native memory-like | SystemVerilog | Apache-2.0 / BSD-2-Clause scopes | Register description; Build manifest; Simulation testbench; Formal collateral | 5e577ee820ff |
| PULP APB I2C15 | APB; I2C | SystemVerilog | Partial licence evidence | Register description; Build manifest | 84855413cc2c |
| wb2axip16 | Wishbone; AXI4; AXI4-Lite; AHB; APB | Verilog | Apache-2.0 | Register description; Build manifest; Formal collateral | 2e8d3bc2d26d |
| LiteSPI17 | Wishbone; CSR; SPI | Python; Generated RTL | BSD-2-Clause | Register description; Build manifest; Simulation testbench | 1efda7b0ffe4 |
| LiteSDCard18 | CSR; LiteX stream; SD | Python; Generated RTL | BSD-2-Clause | Register description; Build manifest; Simulation testbench; Integration example | b68dfded8a76 |
| verilog-ethernet19 | AXI-Stream; MII; GMII; XGMII | Verilog | MIT | Simulation testbench; Timing constraints; Integration example | 77320a9471d1 |
| verilog-axi20 | AXI4; AXI4-Lite | Verilog | MIT | Register description; Build manifest; Simulation testbench | 516bd5dadc33 |
Original compilation data is CC BY 4.0. Each core retains its own licence. The full JSON, CSV and method preserve per-field source references and explicit unknowns.
Read clock, reset and interface evidence together
Clock and reset descriptions become meaningful when connected to the interface’s sequencing requirements. Identify which domain owns a request, when a response can change and what state a reset establishes. A top-level signal declaration is useful structural evidence, but it may not explain the complete operating contract. Follow the linked description and implementation before adopting an assumption.
Where a core has several interfaces, distinguish the control path from the data path. A register-access interface does not necessarily describe the protocol used for a streaming payload. Preserve parameter choices when they alter widths or features. The finder labels summarize the audited record; they are not a substitute for checking the selected elaborated configuration.
Treat collateral as separate evidence types
A register description can make software-visible behavior inspectable. A driver can show how a particular software environment uses that interface. A constraint file can express a timing assumption for a selected setup. Verification collateral can expose stimuli and checks. Those artifacts complement one another, but the presence of one does not prove the claims supplied by the others.
For each located artifact, ask what it actually covers. Does the testbench check a single transaction or a reset during traffic? Does the driver depend on an operating system or platform wrapper? Does a constraint refer to names that exist in the selected configuration? These are questions for an integration test plan, not reasons to convert a null audit field into a negative score.
Pin the revision and retain the unresolved questions
Follow a commit-specific link when revisiting evidence. A branch link can change after an audit, while a permalink identifies the selected revision21. Record later updates as a new snapshot instead of replacing the earlier row without noting that the inspected files changed.
The IP resource finder provides filters over this same evidence. Use it to narrow candidates, then build an original integration example around the actual system boundary. The block-to-SoC guide shows how software-visible actions and independent checks can make selected requirements observable. Neither page supplies a readiness score for these cores.
Use the table viewer to search the same records.
Not covered on this page
- Executing, synthesizing or validating any listed core.
- Security certification or production-readiness rankings.
- Predicting support, integration cost or future maintenance.
- Resolving licence obligations for a particular product.
Sources
Code on this page is original and MIT licensed.
How we test: methodology. Found a mistake? Corrections.