Compare open IP integration evidence

Comparison Last checked 24 October 2026

Compare open IP by the integration evidence available at a pinned revision: clock and reset behavior, interfaces, register descriptions, software, constraints and verification collateral. A repository containing a testbench or driver provides something to inspect, not proof that the core works in your system. Unknown fields below mean this audit did not verify the item at the selected revision.

Begin with the boundary your system must satisfy

Write down the required interface and operating assumptions before comparing rows. An interface name alone leaves timing, widths, parameter choices and optional behavior unresolved. A core that appears suitable from its README may still need an adapter, different reset handling or additional checks at the surrounding system boundary.

The twenty records below use pinned commits and source paths from the cores’ own repositories. Some records share a repository or project family; they are distinct core records, not twenty independent maintenance organizations. The snapshot identifies what was located during this audit rather than estimating each project’s support capacity.

CoreInterfacesLanguageLicence scopeLocated collateralCommit
Ibex1Native request/grantSystemVerilogApache-2.0Register description; Software collateral; Build manifest; Formal collateral; Integration examplea896ef22777a
PicoRV322Native memory; AXI4-Lite; WishboneVerilogISCRegister description; Software collateral; Build manifest; Simulation testbench; Formal collateral; Timing constraints; Integration exampleef203c2b0a3f
NEORV323Wishbone; AXI4 bridgeVHDLBSD-3-ClauseRegister description; Software collateral; Simulation testbench; Integration example7d48364855ca
PULP AXI4AXI4; AXI4-Lite; AXI5 ATOPSystemVerilogSHL-0.51 / Apache-2.0 optionRegister description; Build manifest; Simulation testbench; Integration example70b8e54fd460
LiteEth5Wishbone; AXI4-Lite; Etherbone; AXI-Stream adapterPython; Generated VerilogBSD-2-ClauseRegister description; Build manifest; Simulation testbench; Integration examplecc9a53054bc3
CV32E40P6Native instruction/dataSystemVerilogSHL-0.51 / Apache-2.0 optionRegister description; Build manifest; Simulation testbench; Formal collateral; Timing constraintsb353438ff469
VexRiscv7AXI4; Avalon; WishboneScala; Generated VerilogMITRegister description; Build manifest; Simulation testbench; Integration examplebaf7dc82f855
Microwatt8WishboneVHDLCC-BY-4.0; additional rights caveatBuild manifest; Simulation testbench; Timing constraints; Integration examplef341bed306a9
ZipCPU9Wishbone; AXI4-Lite; AXI4VerilogGPL-3.0Register description; Software collateral; Build manifest; Formal collateral42606d2d6ef5
SERV10Native request/acknowledgeVerilogISCRegister description; Software collateral; Build manifest; Simulation testbench; Timing constraints; Integration examplef200eb2ed7b6
Rocket Chip11TileLink; AXI4; AHB-Lite; APBScala; Generated RTLBSD-3-Clause / Apache-2.0 scopesRegister description; Build manifest; Simulation testbench; Integration exampleece7b9ad544b
OpenTitan AES12TL-ULSystemVerilogApache-2.0Register description; Software collateral; Build manifest; Simulation testbench; Formal collateral478afb033bb2
OpenTitan HMAC13TL-ULSystemVerilogApache-2.0Register description; Software collateral; Build manifest; Simulation testbench; Formal collateral478afb033bb2
Caliptra SHA-51214AHB-Lite; Native memory-likeSystemVerilogApache-2.0 / BSD-2-Clause scopesRegister description; Build manifest; Simulation testbench; Formal collateral5e577ee820ff
PULP APB I2C15APB; I2CSystemVerilogPartial licence evidenceRegister description; Build manifest84855413cc2c
wb2axip16Wishbone; AXI4; AXI4-Lite; AHB; APBVerilogApache-2.0Register description; Build manifest; Formal collateral2e8d3bc2d26d
LiteSPI17Wishbone; CSR; SPIPython; Generated RTLBSD-2-ClauseRegister description; Build manifest; Simulation testbench1efda7b0ffe4
LiteSDCard18CSR; LiteX stream; SDPython; Generated RTLBSD-2-ClauseRegister description; Build manifest; Simulation testbench; Integration exampleb68dfded8a76
verilog-ethernet19AXI-Stream; MII; GMII; XGMIIVerilogMITSimulation testbench; Timing constraints; Integration example77320a9471d1
verilog-axi20AXI4; AXI4-LiteVerilogMITRegister description; Build manifest; Simulation testbench516bd5dadc33

Original compilation data is CC BY 4.0. Each core retains its own licence. The full JSON, CSV and method preserve per-field source references and explicit unknowns.

Read clock, reset and interface evidence together

Clock and reset descriptions become meaningful when connected to the interface’s sequencing requirements. Identify which domain owns a request, when a response can change and what state a reset establishes. A top-level signal declaration is useful structural evidence, but it may not explain the complete operating contract. Follow the linked description and implementation before adopting an assumption.

Where a core has several interfaces, distinguish the control path from the data path. A register-access interface does not necessarily describe the protocol used for a streaming payload. Preserve parameter choices when they alter widths or features. The finder labels summarize the audited record; they are not a substitute for checking the selected elaborated configuration.

Treat collateral as separate evidence types

A register description can make software-visible behavior inspectable. A driver can show how a particular software environment uses that interface. A constraint file can express a timing assumption for a selected setup. Verification collateral can expose stimuli and checks. Those artifacts complement one another, but the presence of one does not prove the claims supplied by the others.

For each located artifact, ask what it actually covers. Does the testbench check a single transaction or a reset during traffic? Does the driver depend on an operating system or platform wrapper? Does a constraint refer to names that exist in the selected configuration? These are questions for an integration test plan, not reasons to convert a null audit field into a negative score.

Pin the revision and retain the unresolved questions

Follow a commit-specific link when revisiting evidence. A branch link can change after an audit, while a permalink identifies the selected revision21. Record later updates as a new snapshot instead of replacing the earlier row without noting that the inspected files changed.

The IP resource finder provides filters over this same evidence. Use it to narrow candidates, then build an original integration example around the actual system boundary. The block-to-SoC guide shows how software-visible actions and independent checks can make selected requirements observable. Neither page supplies a readiness score for these cores.

Use the table viewer to search the same records.

Not covered on this page

Sources

  1. Ibex: inspected source. ↩

  2. PicoRV32: inspected source. ↩

  3. NEORV32: inspected source. ↩

  4. PULP AXI: inspected source. ↩

  5. LiteEth: inspected source. ↩

  6. CV32E40P: inspected source. ↩

  7. VexRiscv: inspected source. ↩

  8. Microwatt: inspected source. ↩

  9. ZipCPU: inspected source. ↩

  10. SERV: inspected source. ↩

  11. Rocket Chip: inspected source. ↩

  12. OpenTitan AES: inspected source. ↩

  13. OpenTitan HMAC: inspected source. ↩

  14. Caliptra SHA-512: inspected source. ↩

  15. PULP APB I2C: inspected source. ↩

  16. wb2axip: inspected source. ↩

  17. LiteSPI: inspected source. ↩

  18. LiteSDCard: inspected source. ↩

  19. verilog-ethernet: inspected source. ↩

  20. verilog-axi: inspected source. ↩

  21. GitHub: Getting permanent links to files. ↩

Code on this page is original and MIT licensed.

How we test: methodology. Found a mistake? Corrections.