Choose a model for mixed-signal verification

Comparison Last tested 24 October 2026

Choose a mixed-signal model by the behavior the test must distinguish, then write down the effects that the model omits. A real-number model can check numeric behavior at digital simulation events, but a passing result does not establish electrical loading, continuous-time dynamics or transistor behavior unless those effects are explicitly represented. Correlate the boundary assumptions before interpreting agreement between tools as agreement with a circuit.

Start with the failure the test must detect

Suppose a controller waits for an analog output to exceed a threshold. A logic-only replacement might expose a ready bit after a fixed delay. That can exercise the controller’s sequencing, yet it cannot reveal a threshold that becomes unreachable after loading the output. A numerical model helps only if its contract includes the loading that causes the problem.

The choice therefore begins with an observable requirement: the value or event, its units, the permitted error and the circumstances in which it matters. State the stimulus and initial condition as well. “The models agree” is incomplete unless the comparison specifies when they were sampled and what disagreement would fail the test.

These are model contracts, not a speed or accuracy ranking. A transistor netlist with inappropriate model parameters can answer the wrong question just as decisively as a simplified model. Conversely, a small equation can answer a deliberately narrow question well. The useful comparison is between the stated requirement and the evidence each representation can produce.

One RC block, two boundary assumptions

The block is a 1 kΩ source resistor feeding a 1 pF capacitor. First the output is unloaded. Then a 1 kΩ resistor is connected from the output to ground. The unloaded step response approaches 1 V with a 1 ns time constant. In the loaded version, the resistor divider makes the final voltage 0.5 V and the parallel resistance seen by the capacitor gives a 0.5 ns time constant.

Those two contracts are encoded explicitly in rc_model.sv. It evaluates the analytical responses at five simulation events, one nanosecond apart. There is no automatic circuit-network solution hidden behind a SystemVerilog real: changing the external load requires changing the model’s parameters or equations. Both simulator runs printed the same values to the displayed precision.

The example folder instructions give exact commands, source pins and hashes. The following complete original file is the one executed. Its checks establish the relationship between the two selected responses; they do not compare against an ngspice process or prove a circuit property over all time.

// SPDX-License-Identifier: MIT
`timescale 1ns/1ps
module rc_model;
  real elapsed_ns;
  real unloaded_voltage;
  real loaded_voltage;
  real final_voltage;
  real effective_tau_ns;
  integer sample;

  function automatic real response(
    input real elapsed,
    input real final_value,
    input real tau
  );
    response = final_value * (1.0 - $exp(-elapsed / tau));
  endfunction

  initial begin
    final_voltage = 0.5;
    effective_tau_ns = 0.5;
    $display("sample elapsed_ns unloaded_rnm_V loaded_rnm_V");
    for (sample = 1; sample <= 5; sample = sample + 1) begin
      #1;
      elapsed_ns = $itor(sample);
      unloaded_voltage = response(elapsed_ns, 1.0, 1.0);
      loaded_voltage = response(
        elapsed_ns, final_voltage, effective_tau_ns
      );
      $display("%0d %0.3f %0.9f %0.9f",
        sample, elapsed_ns, unloaded_voltage, loaded_voltage);
      if (unloaded_voltage <= loaded_voltage)
        $fatal(1, "Loading must reduce voltage in this RC example");
      if (loaded_voltage >= 0.5)
        $fatal(1, "Loaded response must approach its 0.5 V limit");
    end
    $display("CHECK: loaded and unloaded contracts remain distinct");
    $finish;
  end
endmodule

The corresponding ngspice decks solve the same resistor-capacitor block as a circuit. The voltage source rises from 0 to 1 V in 1 ps; the analytical model above assumes an instantaneous step. Both decks request a 1 ps transient output step through 5 ns and sample v(out) at the five named times. ngspice’s manual describes the transient and measurement commands used here¹. Its currently published manual is 47+ development documentation; these executions used release 47.

Save the unloaded deck as unloaded.cir:

Original unloaded RC step
* SPDX-License-Identifier: MIT
Vstep in 0 PULSE(0 1 0 1p 1p 20n 40n)
Rsource in out 1k
Cout out 0 1p
.control
set noaskquit
tran 1p 5n
meas tran sample_1 find v(out) at=1n
meas tran sample_2 find v(out) at=2n
meas tran sample_3 find v(out) at=3n
meas tran sample_4 find v(out) at=4n
meas tran sample_5 find v(out) at=5n
quit
.endc
.end

Save the loaded deck as loaded.cir:

Original loaded RC step
* SPDX-License-Identifier: MIT
Vstep in 0 PULSE(0 1 0 1p 1p 20n 40n)
Rsource in out 1k
Cout out 0 1p
Rload out 0 1k
.control
set noaskquit
tran 1p 5n
meas tran sample_1 find v(out) at=1n
meas tran sample_2 find v(out) at=2n
meas tran sample_3 find v(out) at=3n
meas tran sample_4 find v(out) at=4n
meas tran sample_5 find v(out) at=5n
quit
.endc
.end

Read the discrepancy before changing the tolerance

All table values are volts. RNM columns come from the identical Icarus 13.0 and Verilator 5.052 outputs; circuit columns come from ngspice 47 at its reported 27 °C with ideal R and C elements. The decks’ finite source rise and numerical integration differ from the analytical instantaneous-step assumption.

At 1 ns, comparing the unloaded RNM against the loaded circuit gives a difference of about 0.199856 V. Matching the load assumption reduces that sampled difference to about 0.000067 V. The first discrepancy is dominated by a missing boundary condition; accepting it with a broad tolerance would conceal a different circuit contract. The second comparison is close at these samples, not a claim of exact equality or a global error bound.

Consider a 0.6 V threshold at 1 ns. The unloaded model has already crossed it, while the loaded circuit is below it and its ideal steady-state limit is only 0.5 V. The system-level consequence is different, even though each isolated simulation completed without an error. This threshold illustration is derived from the printed samples and equations; it is not an additional controller simulation.

The public Icarus record, Verilator record and ngspice record retain command outcomes and outputs. No runtime benchmark was collected, so these records cannot support a relative performance claim.

Write the boundary contract before connecting models

Record the physical quantity and reference: voltage relative to which node, current in which direction, and time relative to which event. Specify scaling and legal ranges. A value expressed in millivolts at one boundary and interpreted as volts at another can produce a plausible-looking trace with the wrong threshold decision. Unit conversion belongs in an explicit adapter with its own small checks.

Next define initialization and update behavior. State what a consumer sees before the first valid sample, whether an output holds its previous value, and how reset changes that state. An event-based model needs an update rule; a continuous circuit has behavior between observations. Check the chosen observation times near the decisions that matter rather than comparing only convenient endpoints.

Finally record source and load assumptions in both directions. This example represents one fixed resistive load by replacing the final value and time constant. It has no general bidirectional electrical resolution and no response to a changing load. If the requirement involves switched loading, feedback, saturation or current limiting, either extend and correlate that contract or select a representation that includes those effects.

Keep tool transport errors separate from model disagreement. A missing output, incompatible type or failed compile needs diagnosis before voltage tolerance is meaningful. The simulator observations help interpret the scope of an executed feature check. Preserve rejected constructs and literal diagnostics when a boundary experiment fails; successful compilation alone still says nothing about the physical assumptions.

Where analog-behavioral and transistor models enter

The executed circuit uses ideal linear components, so it is an electrical-network comparison without a transistor model. An analog-behavioral replacement could express an amplifier’s transfer and limiting behavior as equations, but its validity would depend on the effects included and the range checked. A transistor-level version would add the selected circuit topology and device-model assumptions. Neither was executed here.

Choose the next experiment from the missing effect. For example, a load-dependent failure suggests sweeping the load and source behavior; an initialization failure suggests varying initial conditions and the reset sequence. A single close sample is a starting point for correlation, not permission to reuse the model across unrelated operating conditions. Put the comparison envelope and omitted effects beside the model release so a later integration does not silently widen its purpose.

For interface models, the IBIS and AMI reference addresses a different model boundary. Do not infer support for one representation from a result obtained with another, and do not treat a model format’s name as a guarantee that the needed phenomena were supplied.

What current UVM-MS documentation adds

Accellera lists UVM-MS 1.0, dated January 2025, as the current standard; its download page lists companion files modified April 2026². The standard extends UVM’s verification structure into mixed-signal interaction. Its architecture includes a bridge connecting class-side components to the structural signal environment, with proxy, interface and bridge-core responsibilities³.

That framework organizes driving and observing signals; it does not select the RC assumptions above or validate a circuit model automatically. The standard describes analog/mixed-signal and digital/mixed-signal communication and identifies limitations, including particular interface port cases. No UVM-MS package, agent or bridge was executed in this article. Actual integration still needs a versioned feature check against the chosen simulator, representation and bridge implementation.

Not covered on this page

• Transistor, noise, variation, nonlinear or changing-load correlation.
• A closed-loop mixed-signal controller or a UVM-MS execution.
• Commercial-tool speed, accuracy or compatibility rankings.
• A continuous-time error bound between the five reported samples.