EDA tool handoffs: inputs, outputs and versions

Comparison Last checked 24 October 2026

Use this table to identify the documented artifacts a tool accepts and produces before designing a handoff between stages. Matching format names are a starting point, not evidence that two selected versions exchange your design correctly. Preserve the producing command, receiving command and input identity when you test the proposed connection.

Follow an artifact through the proposed flow

A simulation result, a synthesized netlist, a placed design and an analog waveform serve different purposes. Begin with the output needed by the next engineering step, then inspect the producer’s documented output and the consumer’s documented input. The table includes twenty open-source tools across those stages without suggesting that they form one tested end-to-end flow.

Each row records a version identifier or pinned source revision, a licence reference and dated documentation. A repository commit identifies source bytes; it is not necessarily a packaged release or the binary installed on a workstation. When reproducing a tool run, also capture the executable’s reported version and the build or distribution information needed to identify it.

Tool	Stage	Inputs	Outputs	Licence scope	Version / commit
Yosys¹	RTL synthesis	Verilog and synthesizable SystemVerilog subset	Synthesized Verilog netlist in documented example	ISC core; ABC and libraries have separate licences	5053d0e266d9
Verilator²	RTL simulation and lint	Verilog/SystemVerilog	C++/header models, SystemC and JSON	LGPL-3.0-only OR Artistic-2.0 project declaration	1838b6ed035c
cocotb³	Python-driven HDL verification	Python with Verilog/VHDL design sources	Not verified	BSD-3-Clause root licence	259bc580bec8
SBY⁴	Formal verification orchestration	HDL plus .sby configuration	Task logs, status and counterexample trace artifacts	ISC; proof engines have separate licences	79fc9eddca5e
Surelog⁵	SystemVerilog front end	SystemVerilog	UHDM serialized design model	Apache-2.0 root licence	3d52c754a5bc
Icarus Verilog⁶	HDL compilation and simulation	Verilog	Not verified	GPLv2 text in COPYING; per-file exceptions not fully inventoried	4818db887eb1
GHDL⁷	VHDL simulation; experimental synthesis	VHDL	Waveforms; experimental VHDL-1993 synthesized netlist	GPLv2 code; documentation separately licensed	a977191e75d3
NVC⁸	VHDL simulation	VHDL; experimental Verilog	FST waveform in documented example	GPL-3.0-or-later core; specified VHDL libraries Apache-2.0	ef6f527cad74
Verible⁹	SystemVerilog parsing, lint and formatting	SystemVerilog	Concrete syntax tree JSON and formatted source	Apache-2.0 with file-specific third-party notices	0f26265133bd
slang¹⁰	SystemVerilog language front end	SystemVerilog	AST JSON and API model	MIT	eafcf0a60eeb
sv2v¹¹	HDL conversion	SystemVerilog	Verilog source to stdout or files	BSD-3-Clause	493a88f93080
UHDM¹²	Design representation and interchange	SystemVerilog object-model definitions	Persisted UHDM models and C++/VPI API access	Apache-2.0	daa95e1e433a
OpenROAD¹³	ASIC physical design	Verilog netlist plus physical/timing inputs	Physical-design handoff within ORFS; GDSII generation uses KLayout	BSD-3-Clause; PDKs and other tools separately licensed	fb59e23b1dc4
OpenSTA¹⁴	Static timing analysis	Gate-level Verilog and timing constraints	Timing reports through Tcl commands	GPL-3.0 open-source option; separate commercial licence exists	b3e1b3989809
KLayout¹⁵	Layout viewing/editing and checking	Layout databases; Ruby/Python scripting	GDSII/OASIS read/write	Project introduction: GPL-2.0-or-later; repository supplies GPLv3 text	7eb9a25b4224
Magic¹⁶	Layout editing, extraction and DRC	Not verified	GDS/CIF and hierarchical SPICE extraction documented	University of California permissive notice in LICENSE	bed8d4ff8433
Netgen¹⁷	Netlist comparison / LVS	Not verified	Netlist conversions and comparison report	Copying contains GPLv1 text; complete current per-file scope unverified	e5a185dcfa16
nextpnr¹⁸	FPGA place and route	Not verified	iCE40 ASC in documented example; outputs vary by architecture	ISC	22c5adf423ec
FuseSoC¹⁹	HDL package and build orchestration	HDL sources and package metadata	Backend-specific simulation/build products	BSD-2-Clause	2ed5d336467f
ngspice²⁰	Analog/mixed-signal circuit simulation	SPICE netlists and device/model descriptions	Simulation data, voltage/current results and plots	Modified BSD for most code, with exceptions explicitly retained	Official manual 47+ development edition, 2026-09-28

Original compilation data is CC BY 4.0. Tool code and documentation retain their own licences. The JSON, CSV and method retain the fuller fields and source joins behind the compact table.

Distinguish a language from a particular representation

“Verilog” in two rows does not establish that both tools accept the same constructs under the same options. A synthesizable source subset, an elaborated netlist and a testbench are different artifacts even when their filenames share an extension. Record the top, include paths, parameter selections and language mode used for the actual transfer.

The same applies to physical and analog data. A format label leaves questions about units, layer maps, library references and model dependencies unanswered. Treat those as explicit checks for the chosen handoff, not details automatically resolved by a shared suffix. This table keeps documented capability and execution evidence separate so a feature description cannot silently become a compatibility result.

Test one boundary before assembling a larger chain

Start with an original minimal design whose expected outcome is clear. Save the producer’s output, warnings and return code, then run the receiver with a declared configuration. Check what was retained, transformed or rejected. A process completing successfully is useful evidence, but the next check must address the design property you intended to transfer.

For example, preserving a port name is a different observation from preserving a timing constraint or a reset assumption. Choose the checks that matter at that boundary and name them in the result. If a conversion deliberately changes a representation, record the rule and inspect its result rather than requiring byte identity where a transformation is expected.

Keep documentation and measurements dated separately

The documentation audit date describes when these source statements were checked. It does not mean every tool was installed or run on that date. The HDL simulator observations are a separate executed dataset with their own versions, fixture bytes, options and literal outputs.

Use the reproducible handoff guide to record selected inputs and detect changes in a small original package. For a larger flow, keep the input inventory, stage-specific configuration and output checks together. When a tool changes, rerun the affected boundary checks instead of assuming that an unchanged format label preserves the earlier result.

Use the table viewer to search the same records.

Not covered on this page

An end-to-end implementation or tapeout flow.
Compatibility guarantees for the twenty listed tools.
Commercial-tool features or performance rankings.
Project-specific interpretation of upstream licence obligations.

Code on this page is original and MIT licensed.

How we test: methodology. Found a mistake? Corrections.